1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <clk.h> 8 #include <dm.h> 9 #include <debug_uart.h> 10 #include <ram.h> 11 #include <syscon.h> 12 #include <sysmem.h> 13 #include <asm/io.h> 14 #include <asm/arch/vendor.h> 15 #include <misc.h> 16 #include <asm/gpio.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/periph.h> 19 #include <asm/arch/boot_mode.h> 20 #include <asm/arch/rk_atags.h> 21 #include <asm/arch/param.h> 22 #ifdef CONFIG_DM_CHARGE_DISPLAY 23 #include <power/charge_display.h> 24 #endif 25 #ifdef CONFIG_DM_DVFS 26 #include <dvfs.h> 27 #endif 28 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN 29 #include <io-domain.h> 30 #endif 31 #ifdef CONFIG_DM_REGULATOR 32 #include <power/regulator.h> 33 #endif 34 #ifdef CONFIG_DRM_ROCKCHIP 35 #include <video_rockchip.h> 36 #endif 37 #ifdef CONFIG_ROCKCHIP_DEBUGGER 38 #include <rockchip_debugger.h> 39 #endif 40 #include <of_live.h> 41 #include <dm/root.h> 42 #include <console.h> 43 44 DECLARE_GLOBAL_DATA_PTR; 45 /* define serialno max length, the max length is 512 Bytes 46 * The remaining bytes are used to ensure that the first 512 bytes 47 * are valid when executing 'env_set("serial#", value)'. 48 */ 49 #define VENDOR_SN_MAX 513 50 #define CPUID_LEN 0x10 51 #define CPUID_OFF 0x7 52 53 static int rockchip_set_ethaddr(void) 54 { 55 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 56 int ret; 57 u8 ethaddr[ARP_HLEN]; 58 char buf[ARP_HLEN_ASCII + 1]; 59 60 ret = vendor_storage_read(VENDOR_LAN_MAC_ID, ethaddr, sizeof(ethaddr)); 61 if (ret > 0 && is_valid_ethaddr(ethaddr)) { 62 sprintf(buf, "%pM", ethaddr); 63 env_set("ethaddr", buf); 64 } 65 #endif 66 return 0; 67 } 68 69 static int rockchip_set_serialno(void) 70 { 71 char serialno_str[VENDOR_SN_MAX]; 72 int ret = 0, i; 73 u8 cpuid[CPUID_LEN] = {0}; 74 u8 low[CPUID_LEN / 2], high[CPUID_LEN / 2]; 75 u64 serialno; 76 77 /* Read serial number from vendor storage part */ 78 memset(serialno_str, 0, VENDOR_SN_MAX); 79 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 80 ret = vendor_storage_read(VENDOR_SN_ID, serialno_str, (VENDOR_SN_MAX-1)); 81 if (ret > 0) { 82 env_set("serial#", serialno_str); 83 } else { 84 #endif 85 #ifdef CONFIG_ROCKCHIP_EFUSE 86 struct udevice *dev; 87 88 /* retrieve the device */ 89 ret = uclass_get_device_by_driver(UCLASS_MISC, 90 DM_GET_DRIVER(rockchip_efuse), &dev); 91 if (ret) { 92 printf("%s: could not find efuse device\n", __func__); 93 return ret; 94 } 95 /* read the cpu_id range from the efuses */ 96 ret = misc_read(dev, CPUID_OFF, &cpuid, sizeof(cpuid)); 97 if (ret) { 98 printf("%s: reading cpuid from the efuses failed\n", __func__); 99 return ret; 100 } 101 #else 102 /* generate random cpuid */ 103 for (i = 0; i < CPUID_LEN; i++) { 104 cpuid[i] = (u8)(rand()); 105 } 106 #endif 107 /* Generate the serial number based on CPU ID */ 108 for (i = 0; i < 8; i++) { 109 low[i] = cpuid[1 + (i << 1)]; 110 high[i] = cpuid[i << 1]; 111 } 112 serialno = crc32_no_comp(0, low, 8); 113 serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; 114 snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno); 115 116 env_set("serial#", serialno_str); 117 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 118 } 119 #endif 120 return ret; 121 } 122 123 #if defined(CONFIG_USB_FUNCTION_FASTBOOT) 124 int fb_set_reboot_flag(void) 125 { 126 printf("Setting reboot to fastboot flag ...\n"); 127 /* Set boot mode to fastboot */ 128 writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG); 129 130 return 0; 131 } 132 #endif 133 134 __weak int rk_board_init(void) 135 { 136 return 0; 137 } 138 139 __weak int rk_board_late_init(void) 140 { 141 return 0; 142 } 143 144 __weak int soc_clk_dump(void) 145 { 146 return 0; 147 } 148 149 __weak int set_armclk_rate(void) 150 { 151 return 0; 152 } 153 154 int board_late_init(void) 155 { 156 rockchip_set_ethaddr(); 157 rockchip_set_serialno(); 158 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 159 setup_boot_mode(); 160 #endif 161 162 #ifdef CONFIG_DM_CHARGE_DISPLAY 163 charge_display(); 164 #endif 165 166 #ifdef CONFIG_DRM_ROCKCHIP 167 rockchip_show_logo(); 168 #endif 169 170 soc_clk_dump(); 171 172 return rk_board_late_init(); 173 } 174 175 #ifdef CONFIG_USING_KERNEL_DTB 176 #include <asm/arch/resource_img.h> 177 178 int init_kernel_dtb(void) 179 { 180 int ret = 0; 181 ulong fdt_addr = 0; 182 183 fdt_addr = env_get_ulong("fdt_addr_r", 16, 0); 184 if (!fdt_addr) { 185 printf("No Found FDT Load Address.\n"); 186 return -1; 187 } 188 189 ret = rockchip_read_dtb_file((void *)fdt_addr); 190 if (ret < 0) { 191 printf("%s dtb in resource read fail\n", __func__); 192 return 0; 193 } 194 195 of_live_build((void *)fdt_addr, (struct device_node **)&gd->of_root); 196 197 dm_scan_fdt((void *)fdt_addr, false); 198 199 gd->fdt_blob = (void *)fdt_addr; 200 201 /* Reserve 'reserved-memory' */ 202 ret = boot_fdt_add_sysmem_rsv_regions((void *)gd->fdt_blob); 203 if (ret) 204 return ret; 205 206 return 0; 207 } 208 #endif 209 210 void board_env_fixup(void) 211 { 212 ulong kernel_addr_r; 213 214 if (gd->flags & GD_FLG_BL32_ENABLED) 215 return; 216 217 /* If bl32 is disabled, maybe kernel can be load to lower address. */ 218 kernel_addr_r = env_get_ulong("kernel_addr_no_bl32_r", 16, -1); 219 if (kernel_addr_r != -1) 220 env_set_hex("kernel_addr_r", kernel_addr_r); 221 } 222 223 static void early_bootrom_download(void) 224 { 225 if (!tstc()) 226 return; 227 228 gd->console_evt = getc(); 229 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 230 /* ctrl+b */ 231 if (gd->console_evt == CONSOLE_EVT_CTRL_B) { 232 printf("Enter bootrom download..."); 233 mdelay(100); 234 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 235 do_reset(NULL, 0, 0, NULL); 236 printf("failed!\n"); 237 } 238 #endif 239 } 240 241 int board_init(void) 242 { 243 int ret; 244 245 board_debug_uart_init(); 246 early_bootrom_download(); 247 248 #ifdef CONFIG_USING_KERNEL_DTB 249 init_kernel_dtb(); 250 #endif 251 /* 252 * pmucru isn't referenced on some platforms, so pmucru driver can't 253 * probe that the "assigned-clocks" is unused. 254 */ 255 clks_probe(); 256 #ifdef CONFIG_DM_REGULATOR 257 ret = regulators_enable_boot_on(false); 258 if (ret) 259 debug("%s: Cannot enable boot on regulator\n", __func__); 260 #endif 261 262 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN 263 io_domain_init(); 264 #endif 265 266 set_armclk_rate(); 267 268 #ifdef CONFIG_DM_DVFS 269 dvfs_init(true); 270 #endif 271 272 return rk_board_init(); 273 } 274 275 int interrupt_debugger_init(void) 276 { 277 int ret = 0; 278 279 #ifdef CONFIG_ROCKCHIP_DEBUGGER 280 ret = rockchip_debugger_init(); 281 #endif 282 return ret; 283 } 284 285 #if defined(CONFIG_ROCKCHIP_RK1808) && !defined(CONFIG_COPROCESSOR_RK1808) 286 #define PINCTRL_EMMC_BUS8_PATH "/pinctrl/emmc/emmc-bus8" 287 #define PINCTRL_EMMC_CMD_PATH "/pinctrl/emmc/emmc-cmd" 288 #define PINCTRL_EMMC_CLK_PATH "/pinctrl/emmc/emmc-clk" 289 #define PINCTRL_PCFG_PU_2MA_PATH "/pinctrl/pcfg-pull-up-2ma" 290 #define MAX_ROCKCHIP_PINS_ENTRIES 12 291 292 static int rockchip_pinctrl_cfg_fdt_fixup(const char *path, u32 new_phandle) 293 { 294 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 295 const u32 *data; 296 int i, count; 297 int node; 298 299 node = fdt_path_offset(gd->fdt_blob, path); 300 if (node < 0) { 301 debug("%s: can't find: %s\n", __func__, path); 302 return node; 303 } 304 305 data = fdt_getprop(gd->fdt_blob, node, "rockchip,pins", &count); 306 if (!data) { 307 debug("%s: can't find prop \"rockchip,pins\"\n", __func__); 308 return -ENODATA; 309 } 310 311 count /= sizeof(u32); 312 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 313 debug("%s: %d is over max count\n", __func__, count); 314 return -EINVAL; 315 } 316 317 for (i = 0; i < count; i++) 318 cells[i] = data[i]; 319 320 for (i = 0; i < (count >> 2); i++) 321 cells[4 * i + 3] = cpu_to_fdt32(new_phandle); 322 323 fdt_setprop((void *)gd->fdt_blob, node, "rockchip,pins", 324 &cells, count * sizeof(u32)); 325 326 return 0; 327 } 328 #endif 329 330 int board_fdt_fixup(void *blob) 331 { 332 int ret = 0; 333 334 /* 335 * Common fixup for DRM 336 */ 337 #ifdef CONFIG_DRM_ROCKCHIP 338 rockchip_display_fixup(blob); 339 #endif 340 341 /* 342 * Platform fixup: 343 * 344 * - RK3288: Recognize RK3288W by HDMI Revision ID is 0x1A; 345 * - RK1808: MMC strength 2mA; 346 */ 347 #ifdef CONFIG_ROCKCHIP_RK3288 348 if (readl(0xff980004) == 0x1A) { 349 ret = fdt_setprop_string(blob, 0, 350 "compatible", "rockchip,rk3288w"); 351 if (ret) 352 printf("fdt set compatible failed: %d\n", ret); 353 } 354 #elif defined(CONFIG_ROCKCHIP_RK1808) && !defined(CONFIG_COPROCESSOR_RK1808) 355 struct tag *t; 356 u32 ph_pu_2ma; 357 358 t = atags_get_tag(ATAG_SOC_INFO); 359 if (!t) 360 return 0; 361 362 debug("soc=0x%x, flags=0x%x\n", t->u.soc.name, t->u.soc.flags); 363 364 if (t->u.soc.flags != SOC_FLAGS_ET00) 365 return 0; 366 367 ph_pu_2ma = fdt_get_phandle(gd->fdt_blob, 368 fdt_path_offset(gd->fdt_blob, PINCTRL_PCFG_PU_2MA_PATH)); 369 if (!ph_pu_2ma) { 370 debug("Can't find: %s\n", PINCTRL_PCFG_PU_2MA_PATH); 371 return -EINVAL; 372 } 373 374 ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_BUS8_PATH, ph_pu_2ma); 375 ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_CMD_PATH, ph_pu_2ma); 376 ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_CLK_PATH, ph_pu_2ma); 377 #endif 378 379 return ret; 380 } 381 382 #ifdef CONFIG_ARM64_BOOT_AARCH32 383 /* 384 * Fixup MMU region attr for OP-TEE on ARMv8 CPU: 385 * 386 * What ever U-Boot is 64-bit or 32-bit mode, the OP-TEE is always 64-bit mode. 387 * 388 * Command for OP-TEE: 389 * 64-bit mode: dcache is always enabled; 390 * 32-bit mode: dcache is always disabled(Due to some unknown issue); 391 * 392 * Command for U-Boot: 393 * 64-bit mode: MMU table is static defined in rkxxx.c file, all memory 394 * regions are mapped. That's good to match OP-TEE MMU policy. 395 * 396 * 32-bit mode: MMU table is setup according to gd->bd->bi_dram[..] where 397 * the OP-TEE region has been reserved, so it can not be 398 * mapped(i.e. dcache is disabled). That's also good to match 399 * OP-TEE MMU policy. 400 * 401 * For the data coherence when communication between U-Boot and OP-TEE, U-Boot 402 * should follow OP-TEE MMU policy. 403 * 404 * Here is the special: 405 * When CONFIG_ARM64_BOOT_AARCH32 is enabled, U-Boot is 32-bit mode while 406 * OP-TEE is still 64-bit mode. U-Boot would not map MMU table for OP-TEE 407 * region(but OP-TEE requires it cacheable) so we fixup here. 408 */ 409 int board_initr_caches_fixup(void) 410 { 411 struct memblock mem; 412 413 mem = param_parse_optee_mem(); 414 if (mem.size) 415 mmu_set_region_dcache_behaviour(mem.base, mem.size, 416 DCACHE_WRITEBACK); 417 return 0; 418 } 419 #endif 420 421 void board_quiesce_devices(void) 422 { 423 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 424 /* Destroy atags makes next warm boot safer */ 425 atags_destroy(); 426 #endif 427 } 428 429 void enable_caches(void) 430 { 431 icache_enable(); 432 dcache_enable(); 433 } 434 435 #ifdef CONFIG_LMB 436 /* 437 * Using last bi_dram[...] to initialize "bootm_low" and "bootm_mapsize". 438 * This makes lmb_alloc_base() always alloc from tail of sdram. 439 * If we don't assign it, bi_dram[0] is used by default and it may cause 440 * lmb_alloc_base() fail when bi_dram[0] range is small. 441 */ 442 void board_lmb_reserve(struct lmb *lmb) 443 { 444 u64 start, size; 445 char bootm_low[32]; 446 char bootm_mapsize[32]; 447 int i; 448 449 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 450 if (!gd->bd->bi_dram[i].size) 451 break; 452 } 453 454 start = gd->bd->bi_dram[i - 1].start; 455 size = gd->bd->bi_dram[i - 1].size; 456 457 /* 458 * 32-bit kernel: ramdisk/fdt shouldn't be loaded to highmem area(768MB+), 459 * otherwise "Unable to handle kernel paging request at virtual address ...". 460 * 461 * So that we hope limit highest address at 768M, but there comes the the 462 * problem: ramdisk is a compressed image and it expands after descompress, 463 * so it accesses 768MB+ and brings the above "Unable to handle kernel ...". 464 * 465 * We make a appointment that the highest memory address is 512MB, it 466 * makes lmb alloc safer. 467 */ 468 #ifndef CONFIG_ARM64 469 if (start >= ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) { 470 start = gd->bd->bi_dram[i - 2].start; 471 size = gd->bd->bi_dram[i - 2].size; 472 } 473 474 if ((start + size) > ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) 475 size = (u64)CONFIG_SYS_SDRAM_BASE + SZ_512M - start; 476 #endif 477 sprintf(bootm_low, "0x%llx", start); 478 sprintf(bootm_mapsize, "0x%llx", size); 479 env_set("bootm_low", bootm_low); 480 env_set("bootm_mapsize", bootm_mapsize); 481 } 482 #endif 483 484 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \ 485 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS) 486 int board_init_f_init_serial(void) 487 { 488 struct tag *t = atags_get_tag(ATAG_SERIAL); 489 490 if (t) { 491 gd->serial.using_pre_serial = t->u.serial.enable; 492 gd->serial.addr = t->u.serial.addr; 493 gd->serial.baudrate = t->u.serial.baudrate; 494 gd->serial.id = t->u.serial.id; 495 496 debug("%s: enable=%d, addr=0x%lx, baudrate=%d, id=%d\n", 497 __func__, gd->serial.using_pre_serial, 498 gd->serial.addr, gd->serial.baudrate, 499 gd->serial.id); 500 } 501 502 return 0; 503 } 504 #endif 505 506 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) 507 #include <fdt_support.h> 508 #include <usb.h> 509 #include <usb/dwc2_udc.h> 510 511 static struct dwc2_plat_otg_data otg_data = { 512 .rx_fifo_sz = 512, 513 .np_tx_fifo_sz = 16, 514 .tx_fifo_sz = 128, 515 }; 516 517 int board_usb_init(int index, enum usb_init_type init) 518 { 519 int node; 520 fdt_addr_t addr; 521 const fdt32_t *reg; 522 const void *blob = gd->fdt_blob; 523 524 /* find the usb_otg node */ 525 node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); 526 527 retry: 528 if (node > 0) { 529 reg = fdt_getprop(blob, node, "reg", NULL); 530 if (!reg) 531 return -EINVAL; 532 533 addr = fdt_translate_address(blob, node, reg); 534 if (addr == OF_BAD_ADDR) { 535 pr_err("Not found usb_otg address\n"); 536 return -EINVAL; 537 } 538 539 #if defined(CONFIG_ROCKCHIP_RK3288) 540 if (addr != 0xff580000) { 541 node = fdt_node_offset_by_compatible(blob, node, 542 "snps,dwc2"); 543 goto retry; 544 } 545 #endif 546 } else { 547 /* 548 * With kernel dtb support, rk3288 dwc2 otg node 549 * use the rockchip legacy dwc2 driver "dwc_otg_310" 550 * with the compatible "rockchip,rk3288_usb20_otg", 551 * and rk3368 also use the "dwc_otg_310" driver with 552 * the compatible "rockchip,rk3368-usb". 553 */ 554 #if defined(CONFIG_ROCKCHIP_RK3288) 555 node = fdt_node_offset_by_compatible(blob, -1, 556 "rockchip,rk3288_usb20_otg"); 557 #elif defined(CONFIG_ROCKCHIP_RK3368) 558 node = fdt_node_offset_by_compatible(blob, -1, 559 "rockchip,rk3368-usb"); 560 #endif 561 if (node > 0) { 562 goto retry; 563 } else { 564 pr_err("Not found usb_otg device\n"); 565 return -ENODEV; 566 } 567 } 568 569 otg_data.regs_otg = (uintptr_t)addr; 570 571 return dwc2_udc_probe(&otg_data); 572 } 573 574 int board_usb_cleanup(int index, enum usb_init_type init) 575 { 576 return 0; 577 } 578 #endif 579