1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <amp.h> 9 #include <bidram.h> 10 #include <boot_rkimg.h> 11 #include <cli.h> 12 #include <clk.h> 13 #include <console.h> 14 #include <debug_uart.h> 15 #include <dm.h> 16 #include <dvfs.h> 17 #include <io-domain.h> 18 #include <key.h> 19 #include <memblk.h> 20 #include <misc.h> 21 #include <of_live.h> 22 #include <ram.h> 23 #include <rockchip_debugger.h> 24 #include <syscon.h> 25 #include <sysmem.h> 26 #include <video_rockchip.h> 27 #include <asm/io.h> 28 #include <asm/gpio.h> 29 #include <dm/uclass-internal.h> 30 #include <dm/root.h> 31 #include <power/charge_display.h> 32 #include <power/regulator.h> 33 #include <asm/arch/boot_mode.h> 34 #include <asm/arch/clock.h> 35 #include <asm/arch/cpu.h> 36 #include <asm/arch/hotkey.h> 37 #include <asm/arch/param.h> 38 #include <asm/arch/periph.h> 39 #include <asm/arch/resource_img.h> 40 #include <asm/arch/rk_atags.h> 41 #include <asm/arch/vendor.h> 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 __weak int rk_board_late_init(void) 46 { 47 return 0; 48 } 49 50 __weak int rk_board_fdt_fixup(void *blob) 51 { 52 return 0; 53 } 54 55 __weak int soc_clk_dump(void) 56 { 57 return 0; 58 } 59 60 __weak int set_armclk_rate(void) 61 { 62 return 0; 63 } 64 65 __weak int rk_board_init(void) 66 { 67 return 0; 68 } 69 70 /* 71 * define serialno max length, the max length is 512 Bytes 72 * The remaining bytes are used to ensure that the first 512 bytes 73 * are valid when executing 'env_set("serial#", value)'. 74 */ 75 #define VENDOR_SN_MAX 513 76 #define CPUID_LEN 0x10 77 #define CPUID_OFF 0x07 78 79 static int rockchip_set_ethaddr(void) 80 { 81 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 82 char buf[ARP_HLEN_ASCII + 1]; 83 u8 ethaddr[ARP_HLEN]; 84 int ret; 85 86 ret = vendor_storage_read(VENDOR_LAN_MAC_ID, ethaddr, sizeof(ethaddr)); 87 if (ret > 0 && is_valid_ethaddr(ethaddr)) { 88 sprintf(buf, "%pM", ethaddr); 89 env_set("ethaddr", buf); 90 } 91 #endif 92 return 0; 93 } 94 95 static int rockchip_set_serialno(void) 96 { 97 u8 low[CPUID_LEN / 2], high[CPUID_LEN / 2]; 98 u8 cpuid[CPUID_LEN] = {0}; 99 char serialno_str[VENDOR_SN_MAX]; 100 int ret = 0, i; 101 u64 serialno; 102 103 /* Read serial number from vendor storage part */ 104 memset(serialno_str, 0, VENDOR_SN_MAX); 105 106 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 107 ret = vendor_storage_read(VENDOR_SN_ID, serialno_str, (VENDOR_SN_MAX-1)); 108 if (ret > 0) { 109 env_set("serial#", serialno_str); 110 } else { 111 #endif 112 #ifdef CONFIG_ROCKCHIP_EFUSE 113 struct udevice *dev; 114 115 /* retrieve the device */ 116 ret = uclass_get_device_by_driver(UCLASS_MISC, 117 DM_GET_DRIVER(rockchip_efuse), 118 &dev); 119 if (ret) { 120 printf("%s: could not find efuse device\n", __func__); 121 return ret; 122 } 123 124 /* read the cpu_id range from the efuses */ 125 ret = misc_read(dev, CPUID_OFF, &cpuid, sizeof(cpuid)); 126 if (ret) { 127 printf("%s: read cpuid from efuses failed, ret=%d\n", 128 __func__, ret); 129 return ret; 130 } 131 #else 132 /* generate random cpuid */ 133 for (i = 0; i < CPUID_LEN; i++) 134 cpuid[i] = (u8)(rand()); 135 #endif 136 /* Generate the serial number based on CPU ID */ 137 for (i = 0; i < 8; i++) { 138 low[i] = cpuid[1 + (i << 1)]; 139 high[i] = cpuid[i << 1]; 140 } 141 142 serialno = crc32_no_comp(0, low, 8); 143 serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; 144 snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno); 145 146 env_set("serial#", serialno_str); 147 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 148 } 149 #endif 150 151 return ret; 152 } 153 154 #if defined(CONFIG_USB_FUNCTION_FASTBOOT) 155 int fb_set_reboot_flag(void) 156 { 157 printf("Setting reboot to fastboot flag ...\n"); 158 writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG); 159 160 return 0; 161 } 162 #endif 163 164 #ifdef CONFIG_ROCKCHIP_USB_BOOT 165 static int boot_from_udisk(void) 166 { 167 struct blk_desc *desc; 168 char *devtype; 169 char *devnum; 170 171 devtype = env_get("devtype"); 172 devnum = env_get("devnum"); 173 174 /* Booting priority: mmc1 > udisk */ 175 if (!strcmp(devtype, "mmc") && !strcmp(devnum, "1")) 176 return 0; 177 178 if (!run_command("usb start", -1)) { 179 desc = blk_get_devnum_by_type(IF_TYPE_USB, 0); 180 if (!desc) { 181 printf("No usb device found\n"); 182 return -ENODEV; 183 } 184 185 if (!run_command("rkimgtest usb 0", -1)) { 186 rockchip_set_bootdev(desc); 187 env_set("devtype", "usb"); 188 env_set("devnum", "0"); 189 printf("Boot from usb 0\n"); 190 } else { 191 printf("No usb dev 0 found\n"); 192 return -ENODEV; 193 } 194 } 195 196 return 0; 197 } 198 #endif 199 200 static void env_fixup(void) 201 { 202 struct memblock mem; 203 ulong u_addr_r; 204 phys_size_t end; 205 char *addr_r; 206 207 #ifdef ENV_MEM_LAYOUT_SETTINGS1 208 const char *env_addr0[] = { 209 "scriptaddr", "pxefile_addr_r", 210 "fdt_addr_r", "kernel_addr_r", "ramdisk_addr_r", 211 }; 212 const char *env_addr1[] = { 213 "scriptaddr1", "pxefile_addr1_r", 214 "fdt_addr1_r", "kernel_addr1_r", "ramdisk_addr1_r", 215 }; 216 int i; 217 218 /* 128M is a typical ram size for most platform, so as default here */ 219 if (gd->ram_size <= SZ_128M) { 220 /* Replace orignal xxx_addr_r */ 221 for (i = 0; i < ARRAY_SIZE(env_addr1); i++) { 222 addr_r = env_get(env_addr1[i]); 223 if (addr_r) 224 env_set(env_addr0[i], addr_r); 225 } 226 } 227 #endif 228 /* If bl32 is disabled, maybe kernel can be load to lower address. */ 229 if (!(gd->flags & GD_FLG_BL32_ENABLED)) { 230 addr_r = env_get("kernel_addr_no_bl32_r"); 231 if (addr_r) 232 env_set("kernel_addr_r", addr_r); 233 /* If bl32 is enlarged, we move ramdisk addr right behind it */ 234 } else { 235 mem = param_parse_optee_mem(); 236 end = mem.base + mem.size; 237 u_addr_r = env_get_ulong("ramdisk_addr_r", 16, 0); 238 if (u_addr_r >= mem.base && u_addr_r < end) 239 env_set_hex("ramdisk_addr_r", end); 240 } 241 } 242 243 static void cmdline_handle(void) 244 { 245 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 246 struct tag *t; 247 248 t = atags_get_tag(ATAG_PUB_KEY); 249 if (t) { 250 /* Pass if efuse/otp programmed */ 251 if (t->u.pub_key.flag == PUBKEY_FUSE_PROGRAMMED) 252 env_update("bootargs", "fuse.programmed=1"); 253 else 254 env_update("bootargs", "fuse.programmed=0"); 255 } 256 #endif 257 } 258 259 int board_late_init(void) 260 { 261 rockchip_set_ethaddr(); 262 rockchip_set_serialno(); 263 setup_download_mode(); 264 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 265 setup_boot_mode(); 266 #endif 267 #ifdef CONFIG_ROCKCHIP_USB_BOOT 268 boot_from_udisk(); 269 #endif 270 #ifdef CONFIG_DM_CHARGE_DISPLAY 271 charge_display(); 272 #endif 273 #ifdef CONFIG_DRM_ROCKCHIP 274 rockchip_show_logo(); 275 #endif 276 env_fixup(); 277 soc_clk_dump(); 278 cmdline_handle(); 279 280 return rk_board_late_init(); 281 } 282 283 #ifdef CONFIG_USING_KERNEL_DTB 284 /* Here, only fixup cru phandle, pmucru is not included */ 285 static int phandles_fixup_cru(void *fdt) 286 { 287 const char *props[] = { "clocks", "assigned-clocks" }; 288 struct udevice *dev; 289 struct uclass *uc; 290 const char *comp; 291 u32 id, nclocks; 292 u32 *clocks; 293 int phandle, ncells; 294 int off, offset; 295 int ret, length; 296 int i, j; 297 int first_phandle = -1; 298 299 phandle = -ENODATA; 300 ncells = -ENODATA; 301 302 /* fdt points to kernel dtb, getting cru phandle and "#clock-cells" */ 303 for (offset = fdt_next_node(fdt, 0, NULL); 304 offset >= 0; 305 offset = fdt_next_node(fdt, offset, NULL)) { 306 comp = fdt_getprop(fdt, offset, "compatible", NULL); 307 if (!comp) 308 continue; 309 310 /* Actually, this is not a good method to get cru node */ 311 off = strlen(comp) - strlen("-cru"); 312 if (off > 0 && !strncmp(comp + off, "-cru", 4)) { 313 phandle = fdt_get_phandle(fdt, offset); 314 ncells = fdtdec_get_int(fdt, offset, 315 "#clock-cells", -ENODATA); 316 break; 317 } 318 } 319 320 if (phandle == -ENODATA || ncells == -ENODATA) 321 return 0; 322 323 debug("%s: target cru: clock-cells:%d, phandle:0x%x\n", 324 __func__, ncells, fdt32_to_cpu(phandle)); 325 326 /* Try to fixup all cru phandle from U-Boot dtb nodes */ 327 for (id = 0; id < UCLASS_COUNT; id++) { 328 ret = uclass_get(id, &uc); 329 if (ret) 330 continue; 331 332 if (list_empty(&uc->dev_head)) 333 continue; 334 335 list_for_each_entry(dev, &uc->dev_head, uclass_node) { 336 /* Only U-Boot node go further */ 337 if (!dev_read_bool(dev, "u-boot,dm-pre-reloc") && 338 !dev_read_bool(dev, "u-boot,dm-spl")) 339 continue; 340 341 for (i = 0; i < ARRAY_SIZE(props); i++) { 342 if (!dev_read_prop(dev, props[i], &length)) 343 continue; 344 345 clocks = malloc(length); 346 if (!clocks) 347 return -ENOMEM; 348 349 /* Read "props[]" which contains cru phandle */ 350 nclocks = length / sizeof(u32); 351 if (dev_read_u32_array(dev, props[i], 352 clocks, nclocks)) { 353 free(clocks); 354 continue; 355 } 356 357 /* Fixup with kernel cru phandle */ 358 for (j = 0; j < nclocks; j += (ncells + 1)) { 359 /* 360 * Check: update pmucru phandle with cru 361 * phandle by mistake. 362 */ 363 if (first_phandle == -1) 364 first_phandle = clocks[j]; 365 366 if (clocks[j] != first_phandle) { 367 debug("WARN: %s: first cru phandle=%d, this=%d\n", 368 dev_read_name(dev), 369 first_phandle, clocks[j]); 370 continue; 371 } 372 373 clocks[j] = phandle; 374 } 375 376 /* 377 * Override live dt nodes but not fdt nodes, 378 * because all U-Boot nodes has been imported 379 * to live dt nodes, should use "dev_xxx()". 380 */ 381 dev_write_u32_array(dev, props[i], 382 clocks, nclocks); 383 free(clocks); 384 } 385 } 386 } 387 388 return 0; 389 } 390 391 static int phandles_fixup_gpio(void *fdt, void *ufdt) 392 { 393 struct udevice *dev; 394 struct uclass *uc; 395 const char *prop = "gpios"; 396 const char *comp; 397 char *gpio_name[10]; 398 int gpio_off[10]; 399 int pinctrl; 400 int offset; 401 int i = 0; 402 int n = 0; 403 404 pinctrl = fdt_path_offset(fdt, "/pinctrl"); 405 if (pinctrl < 0) 406 return 0; 407 408 memset(gpio_name, 0, sizeof(gpio_name)); 409 for (offset = fdt_first_subnode(fdt, pinctrl); 410 offset >= 0; 411 offset = fdt_next_subnode(fdt, offset)) { 412 /* assume the font nodes are gpio node */ 413 if (++i >= ARRAY_SIZE(gpio_name)) 414 break; 415 416 comp = fdt_getprop(fdt, offset, "compatible", NULL); 417 if (!comp) 418 continue; 419 420 if (!strcmp(comp, "rockchip,gpio-bank")) { 421 gpio_name[n] = (char *)fdt_get_name(fdt, offset, NULL); 422 gpio_off[n] = offset; 423 n++; 424 } 425 } 426 427 if (!gpio_name[0]) 428 return 0; 429 430 if (uclass_get(UCLASS_KEY, &uc) || list_empty(&uc->dev_head)) 431 return 0; 432 433 list_for_each_entry(dev, &uc->dev_head, uclass_node) { 434 u32 new_phd, phd_old; 435 char *name; 436 ofnode ofn; 437 438 if (!dev_read_bool(dev, "u-boot,dm-pre-reloc") && 439 !dev_read_bool(dev, "u-boot,dm-spl")) 440 continue; 441 442 if (dev_read_u32_array(dev, prop, &phd_old, 1)) 443 continue; 444 445 ofn = ofnode_get_by_phandle(phd_old); 446 if (!ofnode_valid(ofn)) 447 continue; 448 449 name = (char *)ofnode_get_name(ofn); 450 if (!name) 451 continue; 452 453 for (i = 0; i < ARRAY_SIZE(gpio_name[i]); i++) { 454 if (gpio_name[i] && !strcmp(name, gpio_name[i])) { 455 new_phd = fdt_get_phandle(fdt, gpio_off[i]); 456 dev_write_u32_array(dev, prop, &new_phd, 1); 457 break; 458 } 459 } 460 } 461 462 return 0; 463 } 464 465 __weak int board_mmc_dm_reinit(struct udevice *dev) 466 { 467 return 0; 468 } 469 470 static int mmc_dm_reinit(void) 471 { 472 struct udevice *dev; 473 struct uclass *uc; 474 int ret; 475 476 if (uclass_get(UCLASS_MMC, &uc) || list_empty(&uc->dev_head)) 477 return 0; 478 479 list_for_each_entry(dev, &uc->dev_head, uclass_node) { 480 ret = board_mmc_dm_reinit(dev); 481 if (ret) 482 return ret; 483 } 484 485 return 0; 486 } 487 488 static void env_fixup_fdt_addr(void) 489 { 490 #ifdef ENV_MEM_LAYOUT_SETTINGS1 491 char *addr_r; 492 493 if (gd->ram_size <= SZ_128M) { 494 addr_r = env_get("fdt_addr1_r"); 495 if (addr_r) 496 env_set("fdt_addr_r", addr_r); 497 } 498 #endif 499 } 500 501 int init_kernel_dtb(void) 502 { 503 ulong fdt_addr; 504 void *ufdt_blob; 505 int ret; 506 507 env_fixup_fdt_addr(); 508 509 fdt_addr = env_get_ulong("fdt_addr_r", 16, 0); 510 if (!fdt_addr) { 511 printf("No Found FDT Load Address.\n"); 512 return -1; 513 } 514 515 ret = rockchip_read_dtb_file((void *)fdt_addr); 516 if (ret < 0) { 517 if (!fdt_check_header(gd->fdt_blob_kern)) { 518 fdt_addr = (ulong)memalign(ARCH_DMA_MINALIGN, 519 fdt_totalsize(gd->fdt_blob_kern)); 520 if (!fdt_addr) 521 return -ENOMEM; 522 523 memcpy((void *)fdt_addr, gd->fdt_blob_kern, 524 fdt_totalsize(gd->fdt_blob_kern)); 525 printf("DTB: embedded kern.dtb\n"); 526 } else { 527 printf("Failed to get kernel dtb, ret=%d\n", ret); 528 return ret; 529 } 530 } 531 532 ufdt_blob = (void *)gd->fdt_blob; 533 gd->fdt_blob = (void *)fdt_addr; 534 535 hotkey_run(HK_FDT); 536 537 /* 538 * There is a phandle miss match between U-Boot and kernel dtb node, 539 * we fixup it in U-Boot live dt nodes. 540 * 541 * CRU: all nodes. 542 * GPIO: key nodes. 543 */ 544 phandles_fixup_cru((void *)gd->fdt_blob); 545 phandles_fixup_gpio((void *)gd->fdt_blob, (void *)ufdt_blob); 546 547 of_live_build((void *)gd->fdt_blob, (struct device_node **)&gd->of_root); 548 dm_scan_fdt((void *)gd->fdt_blob, false); 549 550 /* 551 * There maybe something for the mmc devices to do after kernel dtb 552 * dm setup, eg: regain the clock device binding from kernel dtb. 553 */ 554 mmc_dm_reinit(); 555 556 /* Reserve 'reserved-memory' */ 557 ret = boot_fdt_add_sysmem_rsv_regions((void *)gd->fdt_blob); 558 if (ret) 559 return ret; 560 561 return 0; 562 } 563 #endif 564 565 static void early_download(void) 566 { 567 #if defined(CONFIG_PWRKEY_DNL_TRIGGER_NUM) && \ 568 (CONFIG_PWRKEY_DNL_TRIGGER_NUM > 0) 569 if (pwrkey_download_init()) 570 printf("Pwrkey download init failed\n"); 571 #endif 572 573 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 574 if (is_hotkey(HK_BROM_DNL)) { 575 printf("Enter bootrom download..."); 576 flushc(); 577 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 578 do_reset(NULL, 0, 0, NULL); 579 printf("failed!\n"); 580 } 581 #endif 582 } 583 584 static void board_debug_init(void) 585 { 586 if (!gd->serial.using_pre_serial) 587 board_debug_uart_init(); 588 589 if (tstc()) { 590 gd->console_evt = getc(); 591 if (gd->console_evt <= 0x1a) /* 'z' */ 592 printf("Hotkey: ctrl+%c\n", gd->console_evt + 'a' - 1); 593 } 594 } 595 596 int board_init(void) 597 { 598 board_debug_init(); 599 600 #ifdef DEBUG 601 soc_clk_dump(); 602 #endif 603 604 #ifdef CONFIG_USING_KERNEL_DTB 605 init_kernel_dtb(); 606 #endif 607 early_download(); 608 609 /* 610 * pmucru isn't referenced on some platforms, so pmucru driver can't 611 * probe that the "assigned-clocks" is unused. 612 */ 613 clks_probe(); 614 #ifdef CONFIG_DM_REGULATOR 615 if (regulators_enable_boot_on(is_hotkey(HK_REGULATOR))) 616 debug("%s: Can't enable boot on regulator\n", __func__); 617 #endif 618 619 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN 620 io_domain_init(); 621 #endif 622 623 set_armclk_rate(); 624 625 #ifdef CONFIG_DM_DVFS 626 dvfs_init(true); 627 #endif 628 629 return rk_board_init(); 630 } 631 632 int interrupt_debugger_init(void) 633 { 634 #ifdef CONFIG_ROCKCHIP_DEBUGGER 635 return rockchip_debugger_init(); 636 #else 637 return 0; 638 #endif 639 } 640 641 int board_fdt_fixup(void *blob) 642 { 643 /* Common fixup for DRM */ 644 #ifdef CONFIG_DRM_ROCKCHIP 645 rockchip_display_fixup(blob); 646 #endif 647 648 return rk_board_fdt_fixup(blob); 649 } 650 651 #ifdef CONFIG_ARM64_BOOT_AARCH32 652 /* 653 * Fixup MMU region attr for OP-TEE on ARMv8 CPU: 654 * 655 * What ever U-Boot is 64-bit or 32-bit mode, the OP-TEE is always 64-bit mode. 656 * 657 * Command for OP-TEE: 658 * 64-bit mode: dcache is always enabled; 659 * 32-bit mode: dcache is always disabled(Due to some unknown issue); 660 * 661 * Command for U-Boot: 662 * 64-bit mode: MMU table is static defined in rkxxx.c file, all memory 663 * regions are mapped. That's good to match OP-TEE MMU policy. 664 * 665 * 32-bit mode: MMU table is setup according to gd->bd->bi_dram[..] where 666 * the OP-TEE region has been reserved, so it can not be 667 * mapped(i.e. dcache is disabled). That's also good to match 668 * OP-TEE MMU policy. 669 * 670 * For the data coherence when communication between U-Boot and OP-TEE, U-Boot 671 * should follow OP-TEE MMU policy. 672 * 673 * Here is the special: 674 * When CONFIG_ARM64_BOOT_AARCH32 is enabled, U-Boot is 32-bit mode while 675 * OP-TEE is still 64-bit mode. U-Boot would not map MMU table for OP-TEE 676 * region(but OP-TEE requires it cacheable) so we fixup here. 677 */ 678 int board_initr_caches_fixup(void) 679 { 680 struct memblock mem; 681 682 mem = param_parse_optee_mem(); 683 if (mem.size) 684 mmu_set_region_dcache_behaviour(mem.base, mem.size, 685 DCACHE_WRITEBACK); 686 return 0; 687 } 688 #endif 689 690 void arch_preboot_os(uint32_t bootm_state) 691 { 692 if (bootm_state & BOOTM_STATE_OS_PREP) 693 hotkey_run(HK_CLI_OS_PRE); 694 } 695 696 void board_quiesce_devices(void) 697 { 698 hotkey_run(HK_CMDLINE); 699 hotkey_run(HK_CLI_OS_GO); 700 701 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 702 /* Destroy atags makes next warm boot safer */ 703 atags_destroy(); 704 #endif 705 706 #if defined(CONFIG_CONSOLE_RECORD) 707 /* Print record console data */ 708 console_record_print_purge(); 709 #endif 710 } 711 712 void enable_caches(void) 713 { 714 icache_enable(); 715 dcache_enable(); 716 } 717 718 #ifdef CONFIG_LMB 719 /* 720 * Using last bi_dram[...] to initialize "bootm_low" and "bootm_mapsize". 721 * This makes lmb_alloc_base() always alloc from tail of sdram. 722 * If we don't assign it, bi_dram[0] is used by default and it may cause 723 * lmb_alloc_base() fail when bi_dram[0] range is small. 724 */ 725 void board_lmb_reserve(struct lmb *lmb) 726 { 727 char bootm_mapsize[32]; 728 char bootm_low[32]; 729 u64 start, size; 730 int i; 731 732 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 733 if (!gd->bd->bi_dram[i].size) 734 break; 735 } 736 737 start = gd->bd->bi_dram[i - 1].start; 738 size = gd->bd->bi_dram[i - 1].size; 739 740 /* 741 * 32-bit kernel: ramdisk/fdt shouldn't be loaded to highmem area(768MB+), 742 * otherwise "Unable to handle kernel paging request at virtual address ...". 743 * 744 * So that we hope limit highest address at 768M, but there comes the the 745 * problem: ramdisk is a compressed image and it expands after descompress, 746 * so it accesses 768MB+ and brings the above "Unable to handle kernel ...". 747 * 748 * We make a appointment that the highest memory address is 512MB, it 749 * makes lmb alloc safer. 750 */ 751 #ifndef CONFIG_ARM64 752 if (start >= ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) { 753 start = gd->bd->bi_dram[i - 2].start; 754 size = gd->bd->bi_dram[i - 2].size; 755 } 756 757 if ((start + size) > ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) 758 size = (u64)CONFIG_SYS_SDRAM_BASE + SZ_512M - start; 759 #endif 760 sprintf(bootm_low, "0x%llx", start); 761 sprintf(bootm_mapsize, "0x%llx", size); 762 env_set("bootm_low", bootm_low); 763 env_set("bootm_mapsize", bootm_mapsize); 764 } 765 #endif 766 767 #ifdef CONFIG_BIDRAM 768 int board_bidram_reserve(struct bidram *bidram) 769 { 770 struct memblock mem; 771 int ret; 772 773 /* ATF */ 774 mem = param_parse_atf_mem(); 775 ret = bidram_reserve(MEMBLK_ID_ATF, mem.base, mem.size); 776 if (ret) 777 return ret; 778 779 /* PSTORE/ATAGS/SHM */ 780 mem = param_parse_common_resv_mem(); 781 ret = bidram_reserve(MEMBLK_ID_SHM, mem.base, mem.size); 782 if (ret) 783 return ret; 784 785 /* OP-TEE */ 786 mem = param_parse_optee_mem(); 787 ret = bidram_reserve(MEMBLK_ID_OPTEE, mem.base, mem.size); 788 if (ret) 789 return ret; 790 791 return 0; 792 } 793 794 parse_fn_t board_bidram_parse_fn(void) 795 { 796 return param_parse_ddr_mem; 797 } 798 #endif 799 800 #ifdef CONFIG_ROCKCHIP_AMP 801 void cpu_secondary_init_r(void) 802 { 803 amp_cpus_on(); 804 } 805 #endif 806 807 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \ 808 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS) 809 int board_init_f_init_serial(void) 810 { 811 struct tag *t = atags_get_tag(ATAG_SERIAL); 812 813 if (t) { 814 gd->serial.using_pre_serial = t->u.serial.enable; 815 gd->serial.addr = t->u.serial.addr; 816 gd->serial.baudrate = t->u.serial.baudrate; 817 gd->serial.id = t->u.serial.id; 818 819 debug("%s: enable=%d, addr=0x%lx, baudrate=%d, id=%d\n", 820 __func__, gd->serial.using_pre_serial, 821 gd->serial.addr, gd->serial.baudrate, 822 gd->serial.id); 823 } 824 825 return 0; 826 } 827 #endif 828 829 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) 830 #include <fdt_support.h> 831 #include <usb.h> 832 #include <usb/dwc2_udc.h> 833 834 static struct dwc2_plat_otg_data otg_data = { 835 .rx_fifo_sz = 512, 836 .np_tx_fifo_sz = 16, 837 .tx_fifo_sz = 128, 838 }; 839 840 int board_usb_init(int index, enum usb_init_type init) 841 { 842 const void *blob = gd->fdt_blob; 843 const fdt32_t *reg; 844 fdt_addr_t addr; 845 int node; 846 847 /* find the usb_otg node */ 848 node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); 849 850 retry: 851 if (node > 0) { 852 reg = fdt_getprop(blob, node, "reg", NULL); 853 if (!reg) 854 return -EINVAL; 855 856 addr = fdt_translate_address(blob, node, reg); 857 if (addr == OF_BAD_ADDR) { 858 pr_err("Not found usb_otg address\n"); 859 return -EINVAL; 860 } 861 862 #if defined(CONFIG_ROCKCHIP_RK3288) 863 if (addr != 0xff580000) { 864 node = fdt_node_offset_by_compatible(blob, node, 865 "snps,dwc2"); 866 goto retry; 867 } 868 #endif 869 } else { 870 /* 871 * With kernel dtb support, rk3288 dwc2 otg node 872 * use the rockchip legacy dwc2 driver "dwc_otg_310" 873 * with the compatible "rockchip,rk3288_usb20_otg", 874 * and rk3368 also use the "dwc_otg_310" driver with 875 * the compatible "rockchip,rk3368-usb". 876 */ 877 #if defined(CONFIG_ROCKCHIP_RK3288) 878 node = fdt_node_offset_by_compatible(blob, -1, 879 "rockchip,rk3288_usb20_otg"); 880 #elif defined(CONFIG_ROCKCHIP_RK3368) 881 node = fdt_node_offset_by_compatible(blob, -1, 882 "rockchip,rk3368-usb"); 883 #endif 884 if (node > 0) { 885 goto retry; 886 } else { 887 pr_err("Not found usb_otg device\n"); 888 return -ENODEV; 889 } 890 } 891 892 otg_data.regs_otg = (uintptr_t)addr; 893 894 return dwc2_udc_probe(&otg_data); 895 } 896 897 int board_usb_cleanup(int index, enum usb_init_type init) 898 { 899 return 0; 900 } 901 #endif 902