xref: /rk3399_rockchip-uboot/arch/arm/mach-rockchip/board.c (revision 73b4df6a98d2d973cbf1e2b18947abbdbdb82bc1) 
1 /*
2  * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <amp.h>
9 #include <bidram.h>
10 #include <boot_rkimg.h>
11 #include <cli.h>
12 #include <clk.h>
13 #include <console.h>
14 #include <debug_uart.h>
15 #include <dm.h>
16 #include <dvfs.h>
17 #include <io-domain.h>
18 #include <key.h>
19 #include <memblk.h>
20 #include <misc.h>
21 #include <of_live.h>
22 #include <ram.h>
23 #include <rockchip_debugger.h>
24 #include <syscon.h>
25 #include <sysmem.h>
26 #include <video_rockchip.h>
27 #include <asm/io.h>
28 #include <asm/gpio.h>
29 #include <dm/uclass-internal.h>
30 #include <dm/root.h>
31 #include <power/charge_display.h>
32 #include <power/regulator.h>
33 #include <asm/arch/boot_mode.h>
34 #include <asm/arch/clock.h>
35 #include <asm/arch/cpu.h>
36 #include <asm/arch/hotkey.h>
37 #include <asm/arch/param.h>
38 #include <asm/arch/periph.h>
39 #include <asm/arch/resource_img.h>
40 #include <asm/arch/rk_atags.h>
41 #include <asm/arch/vendor.h>
42 
43 DECLARE_GLOBAL_DATA_PTR;
44 
45 __weak int rk_board_late_init(void)
46 {
47 	return 0;
48 }
49 
50 __weak int rk_board_fdt_fixup(void *blob)
51 {
52 	return 0;
53 }
54 
55 __weak int soc_clk_dump(void)
56 {
57 	return 0;
58 }
59 
60 __weak int set_armclk_rate(void)
61 {
62 	return 0;
63 }
64 
65 __weak int rk_board_init(void)
66 {
67 	return 0;
68 }
69 
70 /*
71  * define serialno max length, the max length is 512 Bytes
72  * The remaining bytes are used to ensure that the first 512 bytes
73  * are valid when executing 'env_set("serial#", value)'.
74  */
75 #define VENDOR_SN_MAX	513
76 #define CPUID_LEN	0x10
77 #define CPUID_OFF	0x07
78 
79 static int rockchip_set_ethaddr(void)
80 {
81 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
82 	char buf[ARP_HLEN_ASCII + 1];
83 	u8 ethaddr[ARP_HLEN];
84 	int ret;
85 
86 	ret = vendor_storage_read(VENDOR_LAN_MAC_ID, ethaddr, sizeof(ethaddr));
87 	if (ret > 0 && is_valid_ethaddr(ethaddr)) {
88 		sprintf(buf, "%pM", ethaddr);
89 		env_set("ethaddr", buf);
90 	}
91 #endif
92 	return 0;
93 }
94 
95 static int rockchip_set_serialno(void)
96 {
97 	u8 low[CPUID_LEN / 2], high[CPUID_LEN / 2];
98 	u8 cpuid[CPUID_LEN] = {0};
99 	char serialno_str[VENDOR_SN_MAX];
100 	int ret = 0, i;
101 	u64 serialno;
102 
103 	/* Read serial number from vendor storage part */
104 	memset(serialno_str, 0, VENDOR_SN_MAX);
105 
106 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
107 	ret = vendor_storage_read(VENDOR_SN_ID, serialno_str, (VENDOR_SN_MAX-1));
108 	if (ret > 0) {
109 		env_set("serial#", serialno_str);
110 	} else {
111 #endif
112 #ifdef CONFIG_ROCKCHIP_EFUSE
113 		struct udevice *dev;
114 
115 		/* retrieve the device */
116 		ret = uclass_get_device_by_driver(UCLASS_MISC,
117 						  DM_GET_DRIVER(rockchip_efuse),
118 						  &dev);
119 		if (ret) {
120 			printf("%s: could not find efuse device\n", __func__);
121 			return ret;
122 		}
123 
124 		/* read the cpu_id range from the efuses */
125 		ret = misc_read(dev, CPUID_OFF, &cpuid, sizeof(cpuid));
126 		if (ret) {
127 			printf("%s: read cpuid from efuses failed, ret=%d\n",
128 			       __func__, ret);
129 			return ret;
130 		}
131 #else
132 		/* generate random cpuid */
133 		for (i = 0; i < CPUID_LEN; i++)
134 			cpuid[i] = (u8)(rand());
135 #endif
136 		/* Generate the serial number based on CPU ID */
137 		for (i = 0; i < 8; i++) {
138 			low[i] = cpuid[1 + (i << 1)];
139 			high[i] = cpuid[i << 1];
140 		}
141 
142 		serialno = crc32_no_comp(0, low, 8);
143 		serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
144 		snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno);
145 
146 		env_set("serial#", serialno_str);
147 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
148 	}
149 #endif
150 
151 	return ret;
152 }
153 
154 #if defined(CONFIG_USB_FUNCTION_FASTBOOT)
155 int fb_set_reboot_flag(void)
156 {
157 	printf("Setting reboot to fastboot flag ...\n");
158 	writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
159 
160 	return 0;
161 }
162 #endif
163 
164 #ifdef CONFIG_ROCKCHIP_USB_BOOT
165 static int boot_from_udisk(void)
166 {
167 	struct blk_desc *desc;
168 	char *devtype;
169 	char *devnum;
170 
171 	devtype = env_get("devtype");
172 	devnum = env_get("devnum");
173 
174 	/* Booting priority: mmc1 > udisk */
175 	if (!strcmp(devtype, "mmc") && !strcmp(devnum, "1"))
176 		return 0;
177 
178 	if (!run_command("usb start", -1)) {
179 		desc = blk_get_devnum_by_type(IF_TYPE_USB, 0);
180 		if (!desc) {
181 			printf("No usb device found\n");
182 			return -ENODEV;
183 		}
184 
185 		if (!run_command("rkimgtest usb 0", -1)) {
186 			rockchip_set_bootdev(desc);
187 			env_set("devtype", "usb");
188 			env_set("devnum", "0");
189 			printf("Boot from usb 0\n");
190 		} else {
191 			printf("No usb dev 0 found\n");
192 			return -ENODEV;
193 		}
194 	}
195 
196 	return 0;
197 }
198 #endif
199 
200 static void cmdline_handle(void)
201 {
202 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
203 	struct tag *t;
204 
205 	t = atags_get_tag(ATAG_PUB_KEY);
206 	if (t) {
207 		/* Pass if efuse/otp programmed */
208 		if (t->u.pub_key.flag == PUBKEY_FUSE_PROGRAMMED)
209 			env_update("bootargs", "fuse.programmed=1");
210 		else
211 			env_update("bootargs", "fuse.programmed=0");
212 	}
213 #endif
214 }
215 
216 int board_late_init(void)
217 {
218 	rockchip_set_ethaddr();
219 	rockchip_set_serialno();
220 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0)
221 	setup_boot_mode();
222 #endif
223 #ifdef CONFIG_ROCKCHIP_USB_BOOT
224 	boot_from_udisk();
225 #endif
226 #ifdef CONFIG_DM_CHARGE_DISPLAY
227 	charge_display();
228 #endif
229 #ifdef CONFIG_DRM_ROCKCHIP
230 	rockchip_show_logo();
231 #endif
232 	soc_clk_dump();
233 	cmdline_handle();
234 
235 	return rk_board_late_init();
236 }
237 
238 #ifdef CONFIG_USING_KERNEL_DTB
239 /* Here, only fixup cru phandle, pmucru is not included */
240 static int phandles_fixup_cru(void *fdt)
241 {
242 	const char *props[] = { "clocks", "assigned-clocks" };
243 	struct udevice *dev;
244 	struct uclass *uc;
245 	const char *comp;
246 	u32 id, nclocks;
247 	u32 *clocks;
248 	int phandle, ncells;
249 	int off, offset;
250 	int ret, length;
251 	int i, j;
252 	int first_phandle = -1;
253 
254 	phandle = -ENODATA;
255 	ncells = -ENODATA;
256 
257 	/* fdt points to kernel dtb, getting cru phandle and "#clock-cells" */
258 	for (offset = fdt_next_node(fdt, 0, NULL);
259 	     offset >= 0;
260 	     offset = fdt_next_node(fdt, offset, NULL)) {
261 		comp = fdt_getprop(fdt, offset, "compatible", NULL);
262 		if (!comp)
263 			continue;
264 
265 		/* Actually, this is not a good method to get cru node */
266 		off = strlen(comp) - strlen("-cru");
267 		if (off > 0 && !strncmp(comp + off, "-cru", 4)) {
268 			phandle = fdt_get_phandle(fdt, offset);
269 			ncells = fdtdec_get_int(fdt, offset,
270 						"#clock-cells", -ENODATA);
271 			break;
272 		}
273 	}
274 
275 	if (phandle == -ENODATA || ncells == -ENODATA)
276 		return 0;
277 
278 	debug("%s: target cru: clock-cells:%d, phandle:0x%x\n",
279 	      __func__, ncells, fdt32_to_cpu(phandle));
280 
281 	/* Try to fixup all cru phandle from U-Boot dtb nodes */
282 	for (id = 0; id < UCLASS_COUNT; id++) {
283 		ret = uclass_get(id, &uc);
284 		if (ret)
285 			continue;
286 
287 		if (list_empty(&uc->dev_head))
288 			continue;
289 
290 		list_for_each_entry(dev, &uc->dev_head, uclass_node) {
291 			/* Only U-Boot node go further */
292 			if (!dev_read_bool(dev, "u-boot,dm-pre-reloc") &&
293 			    !dev_read_bool(dev, "u-boot,dm-spl"))
294 				continue;
295 
296 			for (i = 0; i < ARRAY_SIZE(props); i++) {
297 				if (!dev_read_prop(dev, props[i], &length))
298 					continue;
299 
300 				clocks = malloc(length);
301 				if (!clocks)
302 					return -ENOMEM;
303 
304 				/* Read "props[]" which contains cru phandle */
305 				nclocks = length / sizeof(u32);
306 				if (dev_read_u32_array(dev, props[i],
307 						       clocks, nclocks)) {
308 					free(clocks);
309 					continue;
310 				}
311 
312 				/* Fixup with kernel cru phandle */
313 				for (j = 0; j < nclocks; j += (ncells + 1)) {
314 					/*
315 					 * Check: update pmucru phandle with cru
316 					 * phandle by mistake.
317 					 */
318 					if (first_phandle == -1)
319 						first_phandle = clocks[j];
320 
321 					if (clocks[j] != first_phandle) {
322 						debug("WARN: %s: first cru phandle=%d, this=%d\n",
323 						      dev_read_name(dev),
324 						      first_phandle, clocks[j]);
325 						continue;
326 					}
327 
328 					clocks[j] = phandle;
329 				}
330 
331 				/*
332 				 * Override live dt nodes but not fdt nodes,
333 				 * because all U-Boot nodes has been imported
334 				 * to live dt nodes, should use "dev_xxx()".
335 				 */
336 				dev_write_u32_array(dev, props[i],
337 						    clocks, nclocks);
338 				free(clocks);
339 			}
340 		}
341 	}
342 
343 	return 0;
344 }
345 
346 static int phandles_fixup_gpio(void *fdt, void *ufdt)
347 {
348 	struct udevice *dev;
349 	struct uclass *uc;
350 	const char *prop = "gpios";
351 	const char *comp;
352 	char *gpio_name[10];
353 	int gpio_off[10];
354 	int pinctrl;
355 	int offset;
356 	int i = 0;
357 	int n = 0;
358 
359 	pinctrl = fdt_path_offset(fdt, "/pinctrl");
360 	if (pinctrl < 0)
361 		return 0;
362 
363 	memset(gpio_name, 0, sizeof(gpio_name));
364 	for (offset = fdt_first_subnode(fdt, pinctrl);
365 	     offset >= 0;
366 	     offset = fdt_next_subnode(fdt, offset)) {
367 		/* assume the font nodes are gpio node */
368 		if (++i >= ARRAY_SIZE(gpio_name))
369 			break;
370 
371 		comp = fdt_getprop(fdt, offset, "compatible", NULL);
372 		if (!comp)
373 			continue;
374 
375 		if (!strcmp(comp, "rockchip,gpio-bank")) {
376 			gpio_name[n] = (char *)fdt_get_name(fdt, offset, NULL);
377 			gpio_off[n]  = offset;
378 			n++;
379 		}
380 	}
381 
382 	if (!gpio_name[0])
383 		return 0;
384 
385 	if (uclass_get(UCLASS_KEY, &uc) || list_empty(&uc->dev_head))
386 		return 0;
387 
388 	list_for_each_entry(dev, &uc->dev_head, uclass_node) {
389 		u32 new_phd, phd_old;
390 		char *name;
391 		ofnode ofn;
392 
393 		if (!dev_read_bool(dev, "u-boot,dm-pre-reloc") &&
394 		    !dev_read_bool(dev, "u-boot,dm-spl"))
395 			continue;
396 
397 		if (dev_read_u32_array(dev, prop, &phd_old, 1))
398 			continue;
399 
400 		ofn = ofnode_get_by_phandle(phd_old);
401 		if (!ofnode_valid(ofn))
402 			continue;
403 
404 		name = (char *)ofnode_get_name(ofn);
405 		if (!name)
406 			continue;
407 
408 		for (i = 0; i < ARRAY_SIZE(gpio_name[i]); i++) {
409 			if (gpio_name[i] && !strcmp(name, gpio_name[i])) {
410 				new_phd = fdt_get_phandle(fdt, gpio_off[i]);
411 				dev_write_u32_array(dev, prop, &new_phd, 1);
412 				break;
413 			}
414 		}
415 	}
416 
417 	return 0;
418 }
419 
420 int init_kernel_dtb(void)
421 {
422 	ulong fdt_addr;
423 	void *ufdt_blob;
424 	int ret;
425 
426 	fdt_addr = env_get_ulong("fdt_addr_r", 16, 0);
427 	if (!fdt_addr) {
428 		printf("No Found FDT Load Address.\n");
429 		return -1;
430 	}
431 
432 	ret = rockchip_read_dtb_file((void *)fdt_addr);
433 	if (ret < 0) {
434 		if (!fdt_check_header(gd->fdt_blob_kern)) {
435 			fdt_addr = (ulong)memalign(ARCH_DMA_MINALIGN,
436 					fdt_totalsize(gd->fdt_blob_kern));
437 			if (!fdt_addr)
438 				return -ENOMEM;
439 
440 			memcpy((void *)fdt_addr, gd->fdt_blob_kern,
441 			       fdt_totalsize(gd->fdt_blob_kern));
442 			printf("DTB: embedded kern.dtb\n");
443 		} else {
444 			printf("Failed to get kernel dtb, ret=%d\n", ret);
445 			return ret;
446 		}
447 	}
448 
449 	ufdt_blob = (void *)gd->fdt_blob;
450 	gd->fdt_blob = (void *)fdt_addr;
451 
452 	/*
453 	 * There is a phandle miss match between U-Boot and kernel dtb node,
454 	 * we fixup it in U-Boot live dt nodes.
455 	 *
456 	 * CRU:	 all nodes.
457 	 * GPIO: key nodes.
458 	 */
459 	phandles_fixup_cru((void *)gd->fdt_blob);
460 	phandles_fixup_gpio((void *)gd->fdt_blob, (void *)ufdt_blob);
461 
462 	of_live_build((void *)gd->fdt_blob, (struct device_node **)&gd->of_root);
463 	dm_scan_fdt((void *)gd->fdt_blob, false);
464 
465 	/* Reserve 'reserved-memory' */
466 	ret = boot_fdt_add_sysmem_rsv_regions((void *)gd->fdt_blob);
467 	if (ret)
468 		return ret;
469 
470 	return 0;
471 }
472 #endif
473 
474 void board_env_fixup(void)
475 {
476 	struct memblock mem;
477 	ulong u_addr_r;
478 	phys_size_t end;
479 	char *addr_r;
480 
481 #ifdef ENV_MEM_LAYOUT_SETTINGS1
482 	const char *env_addr0[] = {
483 		"scriptaddr", "pxefile_addr_r",
484 		"fdt_addr_r", "kernel_addr_r", "ramdisk_addr_r",
485 	};
486 	const char *env_addr1[] = {
487 		"scriptaddr1", "pxefile_addr1_r",
488 		"fdt_addr1_r", "kernel_addr1_r", "ramdisk_addr1_r",
489 	};
490 	int i;
491 
492 	/* 128M is a typical ram size for most platform, so as default here */
493 	if (gd->ram_size <= SZ_128M) {
494 		/* Replace orignal xxx_addr_r */
495 		for (i = 0; i < ARRAY_SIZE(env_addr1); i++) {
496 			addr_r = env_get(env_addr1[i]);
497 			if (addr_r)
498 				env_set(env_addr0[i], addr_r);
499 		}
500 	}
501 #endif
502 	/* If bl32 is disabled, maybe kernel can be load to lower address. */
503 	if (!(gd->flags & GD_FLG_BL32_ENABLED)) {
504 		addr_r = env_get("kernel_addr_no_bl32_r");
505 		if (addr_r)
506 			env_set("kernel_addr_r", addr_r);
507 	/* If bl32 is enlarged, we move ramdisk addr right behind it */
508 	} else {
509 		mem = param_parse_optee_mem();
510 		end = mem.base + mem.size;
511 		u_addr_r = env_get_ulong("ramdisk_addr_r", 16, 0);
512 		if (u_addr_r >= mem.base && u_addr_r < end)
513 			env_set_hex("ramdisk_addr_r", end);
514 	}
515 }
516 
517 static void early_download_init(void)
518 {
519 #if defined(CONFIG_PWRKEY_DNL_TRIGGER_NUM) && \
520 		(CONFIG_PWRKEY_DNL_TRIGGER_NUM > 0)
521 	if (pwrkey_download_init())
522 		printf("Pwrkey download init failed\n");
523 #endif
524 
525 	if (!tstc())
526 		return;
527 
528 	gd->console_evt = getc();
529 	if (gd->console_evt <= 0x1a) /* 'z' */
530 		printf("Hotkey: ctrl+%c\n", (gd->console_evt + 'a' - 1));
531 
532 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0)
533 	if (is_hotkey(HK_BROM_DNL)) {
534 		printf("Enter bootrom download...");
535 		flushc();
536 		writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
537 		do_reset(NULL, 0, 0, NULL);
538 		printf("failed!\n");
539 	}
540 #endif
541 }
542 
543 static void board_debug_init(void)
544 {
545 	if (!gd->serial.using_pre_serial)
546 		board_debug_uart_init();
547 }
548 
549 int board_init(void)
550 {
551 	board_debug_init();
552 
553 #ifdef DEBUG
554 	soc_clk_dump();
555 #endif
556 
557 #ifdef CONFIG_USING_KERNEL_DTB
558 	init_kernel_dtb();
559 #endif
560 	early_download_init();
561 
562 	/*
563 	 * pmucru isn't referenced on some platforms, so pmucru driver can't
564 	 * probe that the "assigned-clocks" is unused.
565 	 */
566 	clks_probe();
567 #ifdef CONFIG_DM_REGULATOR
568 	if (regulators_enable_boot_on(is_hotkey(HK_REGULATOR)))
569 		debug("%s: Can't enable boot on regulator\n", __func__);
570 #endif
571 
572 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN
573 	io_domain_init();
574 #endif
575 
576 	set_armclk_rate();
577 
578 #ifdef CONFIG_DM_DVFS
579 	dvfs_init(true);
580 #endif
581 
582 	return rk_board_init();
583 }
584 
585 int interrupt_debugger_init(void)
586 {
587 #ifdef CONFIG_ROCKCHIP_DEBUGGER
588 	return rockchip_debugger_init();
589 #else
590 	return 0;
591 #endif
592 }
593 
594 int board_fdt_fixup(void *blob)
595 {
596 	/* Common fixup for DRM */
597 #ifdef CONFIG_DRM_ROCKCHIP
598 	rockchip_display_fixup(blob);
599 #endif
600 
601 	return rk_board_fdt_fixup(blob);
602 }
603 
604 #ifdef CONFIG_ARM64_BOOT_AARCH32
605 /*
606  * Fixup MMU region attr for OP-TEE on ARMv8 CPU:
607  *
608  * What ever U-Boot is 64-bit or 32-bit mode, the OP-TEE is always 64-bit mode.
609  *
610  * Command for OP-TEE:
611  *	64-bit mode: dcache is always enabled;
612  *	32-bit mode: dcache is always disabled(Due to some unknown issue);
613  *
614  * Command for U-Boot:
615  *	64-bit mode: MMU table is static defined in rkxxx.c file, all memory
616  *		     regions are mapped. That's good to match OP-TEE MMU policy.
617  *
618  *	32-bit mode: MMU table is setup according to gd->bd->bi_dram[..] where
619  *		     the OP-TEE region has been reserved, so it can not be
620  *		     mapped(i.e. dcache is disabled). That's also good to match
621  *		     OP-TEE MMU policy.
622  *
623  * For the data coherence when communication between U-Boot and OP-TEE, U-Boot
624  * should follow OP-TEE MMU policy.
625  *
626  * Here is the special:
627  *	When CONFIG_ARM64_BOOT_AARCH32 is enabled, U-Boot is 32-bit mode while
628  *	OP-TEE is still 64-bit mode. U-Boot would not map MMU table for OP-TEE
629  *	region(but OP-TEE requires it cacheable) so we fixup here.
630  */
631 int board_initr_caches_fixup(void)
632 {
633 	struct memblock mem;
634 
635 	mem = param_parse_optee_mem();
636 	if (mem.size)
637 		mmu_set_region_dcache_behaviour(mem.base, mem.size,
638 						DCACHE_WRITEBACK);
639 	return 0;
640 }
641 #endif
642 
643 void arch_preboot_os(uint32_t bootm_state)
644 {
645 	if (bootm_state & BOOTM_STATE_OS_PREP)
646 		hotkey_run(HK_CLI_OS_PRE);
647 }
648 
649 void board_quiesce_devices(void)
650 {
651 	hotkey_run(HK_CMDLINE);
652 	hotkey_run(HK_CLI_OS_GO);
653 
654 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
655 	/* Destroy atags makes next warm boot safer */
656 	atags_destroy();
657 #endif
658 
659 #if defined(CONFIG_CONSOLE_RECORD)
660 	/* Print record console data */
661 	console_record_print_purge();
662 #endif
663 }
664 
665 void enable_caches(void)
666 {
667 	icache_enable();
668 	dcache_enable();
669 }
670 
671 #ifdef CONFIG_LMB
672 /*
673  * Using last bi_dram[...] to initialize "bootm_low" and "bootm_mapsize".
674  * This makes lmb_alloc_base() always alloc from tail of sdram.
675  * If we don't assign it, bi_dram[0] is used by default and it may cause
676  * lmb_alloc_base() fail when bi_dram[0] range is small.
677  */
678 void board_lmb_reserve(struct lmb *lmb)
679 {
680 	char bootm_mapsize[32];
681 	char bootm_low[32];
682 	u64 start, size;
683 	int i;
684 
685 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
686 		if (!gd->bd->bi_dram[i].size)
687 			break;
688 	}
689 
690 	start = gd->bd->bi_dram[i - 1].start;
691 	size = gd->bd->bi_dram[i - 1].size;
692 
693 	/*
694 	 * 32-bit kernel: ramdisk/fdt shouldn't be loaded to highmem area(768MB+),
695 	 * otherwise "Unable to handle kernel paging request at virtual address ...".
696 	 *
697 	 * So that we hope limit highest address at 768M, but there comes the the
698 	 * problem: ramdisk is a compressed image and it expands after descompress,
699 	 * so it accesses 768MB+ and brings the above "Unable to handle kernel ...".
700 	 *
701 	 * We make a appointment that the highest memory address is 512MB, it
702 	 * makes lmb alloc safer.
703 	 */
704 #ifndef CONFIG_ARM64
705 	if (start >= ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) {
706 		start = gd->bd->bi_dram[i - 2].start;
707 		size = gd->bd->bi_dram[i - 2].size;
708 	}
709 
710 	if ((start + size) > ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M))
711 		size = (u64)CONFIG_SYS_SDRAM_BASE + SZ_512M - start;
712 #endif
713 	sprintf(bootm_low, "0x%llx", start);
714 	sprintf(bootm_mapsize, "0x%llx", size);
715 	env_set("bootm_low", bootm_low);
716 	env_set("bootm_mapsize", bootm_mapsize);
717 }
718 #endif
719 
720 #ifdef CONFIG_BIDRAM
721 int board_bidram_reserve(struct bidram *bidram)
722 {
723 	struct memblock mem;
724 	int ret;
725 
726 	/* ATF */
727 	mem = param_parse_atf_mem();
728 	ret = bidram_reserve(MEMBLK_ID_ATF, mem.base, mem.size);
729 	if (ret)
730 		return ret;
731 
732 	/* PSTORE/ATAGS/SHM */
733 	mem = param_parse_common_resv_mem();
734 	ret = bidram_reserve(MEMBLK_ID_SHM, mem.base, mem.size);
735 	if (ret)
736 		return ret;
737 
738 	/* OP-TEE */
739 	mem = param_parse_optee_mem();
740 	ret = bidram_reserve(MEMBLK_ID_OPTEE, mem.base, mem.size);
741 	if (ret)
742 		return ret;
743 
744 	return 0;
745 }
746 
747 parse_fn_t board_bidram_parse_fn(void)
748 {
749 	return param_parse_ddr_mem;
750 }
751 #endif
752 
753 #ifdef CONFIG_ROCKCHIP_AMP
754 void cpu_secondary_init_r(void)
755 {
756 	amp_cpus_on();
757 }
758 #endif
759 
760 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \
761     defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS)
762 int board_init_f_init_serial(void)
763 {
764 	struct tag *t = atags_get_tag(ATAG_SERIAL);
765 
766 	if (t) {
767 		gd->serial.using_pre_serial = t->u.serial.enable;
768 		gd->serial.addr = t->u.serial.addr;
769 		gd->serial.baudrate = t->u.serial.baudrate;
770 		gd->serial.id = t->u.serial.id;
771 
772 		debug("%s: enable=%d, addr=0x%lx, baudrate=%d, id=%d\n",
773 		      __func__, gd->serial.using_pre_serial,
774 		      gd->serial.addr, gd->serial.baudrate,
775 		      gd->serial.id);
776 	}
777 
778 	return 0;
779 }
780 #endif
781 
782 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
783 #include <fdt_support.h>
784 #include <usb.h>
785 #include <usb/dwc2_udc.h>
786 
787 static struct dwc2_plat_otg_data otg_data = {
788 	.rx_fifo_sz	= 512,
789 	.np_tx_fifo_sz	= 16,
790 	.tx_fifo_sz	= 128,
791 };
792 
793 int board_usb_init(int index, enum usb_init_type init)
794 {
795 	const void *blob = gd->fdt_blob;
796 	const fdt32_t *reg;
797 	fdt_addr_t addr;
798 	int node;
799 
800 	/* find the usb_otg node */
801 	node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2");
802 
803 retry:
804 	if (node > 0) {
805 		reg = fdt_getprop(blob, node, "reg", NULL);
806 		if (!reg)
807 			return -EINVAL;
808 
809 		addr = fdt_translate_address(blob, node, reg);
810 		if (addr == OF_BAD_ADDR) {
811 			pr_err("Not found usb_otg address\n");
812 			return -EINVAL;
813 		}
814 
815 #if defined(CONFIG_ROCKCHIP_RK3288)
816 		if (addr != 0xff580000) {
817 			node = fdt_node_offset_by_compatible(blob, node,
818 							     "snps,dwc2");
819 			goto retry;
820 		}
821 #endif
822 	} else {
823 		/*
824 		 * With kernel dtb support, rk3288 dwc2 otg node
825 		 * use the rockchip legacy dwc2 driver "dwc_otg_310"
826 		 * with the compatible "rockchip,rk3288_usb20_otg",
827 		 * and rk3368 also use the "dwc_otg_310" driver with
828 		 * the compatible "rockchip,rk3368-usb".
829 		 */
830 #if defined(CONFIG_ROCKCHIP_RK3288)
831 		node = fdt_node_offset_by_compatible(blob, -1,
832 				"rockchip,rk3288_usb20_otg");
833 #elif defined(CONFIG_ROCKCHIP_RK3368)
834 		node = fdt_node_offset_by_compatible(blob, -1,
835 				"rockchip,rk3368-usb");
836 #endif
837 		if (node > 0) {
838 			goto retry;
839 		} else {
840 			pr_err("Not found usb_otg device\n");
841 			return -ENODEV;
842 		}
843 	}
844 
845 	otg_data.regs_otg = (uintptr_t)addr;
846 
847 	return dwc2_udc_probe(&otg_data);
848 }
849 
850 int board_usb_cleanup(int index, enum usb_init_type init)
851 {
852 	return 0;
853 }
854 #endif
855