xref: /rk3399_rockchip-uboot/arch/arm/mach-rockchip/board.c (revision 6184121cdc2fc45e350eb406a78dbf685f281d2e) 
1 /*
2  * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 #include <common.h>
7 #include <amp.h>
8 #include <clk.h>
9 #include <bidram.h>
10 #include <dm.h>
11 #include <debug_uart.h>
12 #include <memblk.h>
13 #include <ram.h>
14 #include <syscon.h>
15 #include <sysmem.h>
16 #include <asm/io.h>
17 #include <asm/arch/vendor.h>
18 #include <misc.h>
19 #include <asm/gpio.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/cpu.h>
22 #include <asm/arch/periph.h>
23 #include <asm/arch/boot_mode.h>
24 #include <asm/arch/hotkey.h>
25 #include <asm/arch/rk_atags.h>
26 #include <asm/arch/param.h>
27 #ifdef CONFIG_DM_CHARGE_DISPLAY
28 #include <power/charge_display.h>
29 #endif
30 #ifdef CONFIG_DM_DVFS
31 #include <dvfs.h>
32 #endif
33 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN
34 #include <io-domain.h>
35 #endif
36 #ifdef CONFIG_DM_REGULATOR
37 #include <power/regulator.h>
38 #endif
39 #ifdef CONFIG_DRM_ROCKCHIP
40 #include <video_rockchip.h>
41 #endif
42 #ifdef CONFIG_ROCKCHIP_DEBUGGER
43 #include <rockchip_debugger.h>
44 #endif
45 #include <of_live.h>
46 #include <dm/root.h>
47 #include <console.h>
48 
49 DECLARE_GLOBAL_DATA_PTR;
50 /* define serialno max length, the max length is 512 Bytes
51  * The remaining bytes are used to ensure that the first 512 bytes
52  * are valid when executing 'env_set("serial#", value)'.
53  */
54 #define VENDOR_SN_MAX	513
55 #define CPUID_LEN       0x10
56 #define CPUID_OFF       0x7
57 
58 static int rockchip_set_ethaddr(void)
59 {
60 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
61 	int ret;
62 	u8 ethaddr[ARP_HLEN];
63 	char buf[ARP_HLEN_ASCII + 1];
64 
65 	ret = vendor_storage_read(VENDOR_LAN_MAC_ID, ethaddr, sizeof(ethaddr));
66 	if (ret > 0 && is_valid_ethaddr(ethaddr)) {
67 		sprintf(buf, "%pM", ethaddr);
68 		env_set("ethaddr", buf);
69 	}
70 #endif
71 	return 0;
72 }
73 
74 static int rockchip_set_serialno(void)
75 {
76 	char serialno_str[VENDOR_SN_MAX];
77 	int ret = 0, i;
78 	u8 cpuid[CPUID_LEN] = {0};
79 	u8 low[CPUID_LEN / 2], high[CPUID_LEN / 2];
80 	u64 serialno;
81 
82 	/* Read serial number from vendor storage part */
83 	memset(serialno_str, 0, VENDOR_SN_MAX);
84 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
85 	ret = vendor_storage_read(VENDOR_SN_ID, serialno_str, (VENDOR_SN_MAX-1));
86 	if (ret > 0) {
87 		env_set("serial#", serialno_str);
88 	} else {
89 #endif
90 #ifdef CONFIG_ROCKCHIP_EFUSE
91 		struct udevice *dev;
92 
93 		/* retrieve the device */
94 		ret = uclass_get_device_by_driver(UCLASS_MISC,
95 						  DM_GET_DRIVER(rockchip_efuse), &dev);
96 		if (ret) {
97 			printf("%s: could not find efuse device\n", __func__);
98 			return ret;
99 		}
100 		/* read the cpu_id range from the efuses */
101 		ret = misc_read(dev, CPUID_OFF, &cpuid, sizeof(cpuid));
102 		if (ret) {
103 			printf("%s: reading cpuid from the efuses failed\n", __func__);
104 			return ret;
105 		}
106 #else
107 		/* generate random cpuid */
108 		for (i = 0; i < CPUID_LEN; i++) {
109 			cpuid[i] = (u8)(rand());
110 		}
111 #endif
112 		/* Generate the serial number based on CPU ID */
113 		for (i = 0; i < 8; i++) {
114 			low[i] = cpuid[1 + (i << 1)];
115 			high[i] = cpuid[i << 1];
116 		}
117 		serialno = crc32_no_comp(0, low, 8);
118 		serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
119 		snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno);
120 
121 		env_set("serial#", serialno_str);
122 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
123 	}
124 #endif
125 	return ret;
126 }
127 
128 #if defined(CONFIG_USB_FUNCTION_FASTBOOT)
129 int fb_set_reboot_flag(void)
130 {
131 	printf("Setting reboot to fastboot flag ...\n");
132 	/* Set boot mode to fastboot */
133 	writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
134 
135 	return 0;
136 }
137 #endif
138 
139 __weak int rk_board_init(void)
140 {
141 	return 0;
142 }
143 
144 __weak int rk_board_late_init(void)
145 {
146 	return 0;
147 }
148 
149 __weak int soc_clk_dump(void)
150 {
151 	return 0;
152 }
153 
154 __weak int set_armclk_rate(void)
155 {
156 	return 0;
157 }
158 
159 int board_late_init(void)
160 {
161 	rockchip_set_ethaddr();
162 	rockchip_set_serialno();
163 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0)
164 	setup_boot_mode();
165 #endif
166 
167 #ifdef CONFIG_DM_CHARGE_DISPLAY
168 	charge_display();
169 #endif
170 
171 #ifdef CONFIG_DRM_ROCKCHIP
172 	rockchip_show_logo();
173 #endif
174 
175 	soc_clk_dump();
176 
177 	return rk_board_late_init();
178 }
179 
180 #ifdef CONFIG_USING_KERNEL_DTB
181 #include <asm/arch/resource_img.h>
182 
183 int init_kernel_dtb(void)
184 {
185 	int ret = 0;
186 	ulong fdt_addr = 0;
187 
188 	fdt_addr = env_get_ulong("fdt_addr_r", 16, 0);
189 	if (!fdt_addr) {
190 		printf("No Found FDT Load Address.\n");
191 		return -1;
192 	}
193 
194 	ret = rockchip_read_dtb_file((void *)fdt_addr);
195 	if (ret < 0) {
196 		printf("%s dtb in resource read fail\n", __func__);
197 		return 0;
198 	}
199 
200 	of_live_build((void *)fdt_addr, (struct device_node **)&gd->of_root);
201 
202 	dm_scan_fdt((void *)fdt_addr, false);
203 
204 	gd->fdt_blob = (void *)fdt_addr;
205 
206 	/* Reserve 'reserved-memory' */
207 	ret = boot_fdt_add_sysmem_rsv_regions((void *)gd->fdt_blob);
208 	if (ret)
209 		return ret;
210 
211 	return 0;
212 }
213 #endif
214 
215 void board_env_fixup(void)
216 {
217 	ulong kernel_addr_r;
218 
219 	if (gd->flags & GD_FLG_BL32_ENABLED)
220 		return;
221 
222 	/* If bl32 is disabled, maybe kernel can be load to lower address. */
223 	kernel_addr_r = env_get_ulong("kernel_addr_no_bl32_r", 16, -1);
224 	if (kernel_addr_r != -1)
225 		env_set_hex("kernel_addr_r", kernel_addr_r);
226 }
227 
228 static void early_bootrom_download(void)
229 {
230 	if (!tstc())
231 		return;
232 
233 	gd->console_evt = getc();
234 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0)
235 	/* ctrl+b */
236 	if (is_hotkey(HK_BROM_DNL)) {
237 		printf("Enter bootrom download...");
238 		flushc();
239 		writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
240 		do_reset(NULL, 0, 0, NULL);
241 		printf("failed!\n");
242 	}
243 #endif
244 }
245 
246 int board_init(void)
247 {
248 	int ret;
249 
250 	board_debug_uart_init();
251 	early_bootrom_download();
252 
253 #ifdef CONFIG_USING_KERNEL_DTB
254 	init_kernel_dtb();
255 #endif
256 	/*
257 	 * pmucru isn't referenced on some platforms, so pmucru driver can't
258 	 * probe that the "assigned-clocks" is unused.
259 	 */
260 	clks_probe();
261 #ifdef CONFIG_DM_REGULATOR
262 	ret = regulators_enable_boot_on(false);
263 	if (ret)
264 		debug("%s: Cannot enable boot on regulator\n", __func__);
265 #endif
266 
267 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN
268 	io_domain_init();
269 #endif
270 
271 	set_armclk_rate();
272 
273 #ifdef CONFIG_DM_DVFS
274 	dvfs_init(true);
275 #endif
276 
277 	return rk_board_init();
278 }
279 
280 int interrupt_debugger_init(void)
281 {
282 	int ret = 0;
283 
284 #ifdef CONFIG_ROCKCHIP_DEBUGGER
285 	ret = rockchip_debugger_init();
286 #endif
287 	return ret;
288 }
289 
290 #if defined(CONFIG_ROCKCHIP_RK1808) && !defined(CONFIG_COPROCESSOR_RK1808)
291 #define PINCTRL_EMMC_BUS8_PATH		"/pinctrl/emmc/emmc-bus8"
292 #define PINCTRL_EMMC_CMD_PATH		"/pinctrl/emmc/emmc-cmd"
293 #define PINCTRL_EMMC_CLK_PATH		"/pinctrl/emmc/emmc-clk"
294 #define PINCTRL_PCFG_PU_2MA_PATH	"/pinctrl/pcfg-pull-up-2ma"
295 #define MAX_ROCKCHIP_PINS_ENTRIES	12
296 
297 static int rockchip_pinctrl_cfg_fdt_fixup(const char *path, u32 new_phandle)
298 {
299 	u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4];
300 	const u32 *data;
301 	int i, count;
302 	int node;
303 
304 	node = fdt_path_offset(gd->fdt_blob, path);
305 	if (node < 0) {
306 		debug("%s: can't find: %s\n", __func__, path);
307 		return node;
308 	}
309 
310 	data = fdt_getprop(gd->fdt_blob, node, "rockchip,pins", &count);
311 	if (!data) {
312 		debug("%s: can't find prop \"rockchip,pins\"\n", __func__);
313 		return -ENODATA;
314 	}
315 
316 	count /= sizeof(u32);
317 	if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) {
318 		debug("%s: %d is over max count\n", __func__, count);
319 		return -EINVAL;
320 	}
321 
322 	for (i = 0; i < count; i++)
323 		cells[i] = data[i];
324 
325 	for (i = 0; i < (count >> 2); i++)
326 		cells[4 * i + 3] = cpu_to_fdt32(new_phandle);
327 
328 	fdt_setprop((void *)gd->fdt_blob, node, "rockchip,pins",
329 		    &cells, count * sizeof(u32));
330 
331 	return 0;
332 }
333 #endif
334 
335 int board_fdt_fixup(void *blob)
336 {
337 	int ret = 0;
338 
339 	/*
340 	 * Common fixup for DRM
341 	 */
342 #ifdef CONFIG_DRM_ROCKCHIP
343 	rockchip_display_fixup(blob);
344 #endif
345 
346 	/*
347 	 * Platform fixup:
348 	 *
349 	 * - RK3288: Recognize RK3288W by HDMI Revision ID is 0x1A;
350 	 * - RK1808: MMC strength 2mA;
351 	 */
352 #ifdef CONFIG_ROCKCHIP_RK3288
353 	if (soc_is_rk3288w()) {
354 		ret = fdt_setprop_string(blob, 0,
355 					 "compatible", "rockchip,rk3288w");
356 		if (ret)
357 			printf("fdt set compatible failed: %d\n", ret);
358 	}
359 #elif defined(CONFIG_ROCKCHIP_RK1808) && !defined(CONFIG_COPROCESSOR_RK1808)
360 	struct tag *t;
361 	u32 ph_pu_2ma;
362 
363 	t = atags_get_tag(ATAG_SOC_INFO);
364 	if (!t)
365 		return 0;
366 
367 	debug("soc=0x%x, flags=0x%x\n", t->u.soc.name, t->u.soc.flags);
368 
369 	if (t->u.soc.flags != SOC_FLAGS_ET00)
370 		return 0;
371 
372 	ph_pu_2ma = fdt_get_phandle(gd->fdt_blob,
373 		    fdt_path_offset(gd->fdt_blob, PINCTRL_PCFG_PU_2MA_PATH));
374 	if (!ph_pu_2ma) {
375 		debug("Can't find: %s\n", PINCTRL_PCFG_PU_2MA_PATH);
376 		return -EINVAL;
377 	}
378 
379 	ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_BUS8_PATH, ph_pu_2ma);
380 	ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_CMD_PATH, ph_pu_2ma);
381 	ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_CLK_PATH, ph_pu_2ma);
382 #endif
383 
384 	return ret;
385 }
386 
387 #ifdef CONFIG_ARM64_BOOT_AARCH32
388 /*
389  * Fixup MMU region attr for OP-TEE on ARMv8 CPU:
390  *
391  * What ever U-Boot is 64-bit or 32-bit mode, the OP-TEE is always 64-bit mode.
392  *
393  * Command for OP-TEE:
394  *	64-bit mode: dcache is always enabled;
395  *	32-bit mode: dcache is always disabled(Due to some unknown issue);
396  *
397  * Command for U-Boot:
398  *	64-bit mode: MMU table is static defined in rkxxx.c file, all memory
399  *		     regions are mapped. That's good to match OP-TEE MMU policy.
400  *
401  *	32-bit mode: MMU table is setup according to gd->bd->bi_dram[..] where
402  *		     the OP-TEE region has been reserved, so it can not be
403  *		     mapped(i.e. dcache is disabled). That's also good to match
404  *		     OP-TEE MMU policy.
405  *
406  * For the data coherence when communication between U-Boot and OP-TEE, U-Boot
407  * should follow OP-TEE MMU policy.
408  *
409  * Here is the special:
410  *	When CONFIG_ARM64_BOOT_AARCH32 is enabled, U-Boot is 32-bit mode while
411  *	OP-TEE is still 64-bit mode. U-Boot would not map MMU table for OP-TEE
412  *	region(but OP-TEE requires it cacheable) so we fixup here.
413  */
414 int board_initr_caches_fixup(void)
415 {
416 	struct memblock mem;
417 
418 	mem = param_parse_optee_mem();
419 	if (mem.size)
420 		mmu_set_region_dcache_behaviour(mem.base, mem.size,
421 						DCACHE_WRITEBACK);
422 	return 0;
423 }
424 #endif
425 
426 void board_quiesce_devices(void)
427 {
428 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
429 	/* Destroy atags makes next warm boot safer */
430 	atags_destroy();
431 #endif
432 
433 #if defined(CONFIG_CONSOLE_RECORD)
434 	/* Print record console data */
435 	console_record_print_purge();
436 #endif
437 }
438 
439 void enable_caches(void)
440 {
441 	icache_enable();
442 	dcache_enable();
443 }
444 
445 #ifdef CONFIG_LMB
446 /*
447  * Using last bi_dram[...] to initialize "bootm_low" and "bootm_mapsize".
448  * This makes lmb_alloc_base() always alloc from tail of sdram.
449  * If we don't assign it, bi_dram[0] is used by default and it may cause
450  * lmb_alloc_base() fail when bi_dram[0] range is small.
451  */
452 void board_lmb_reserve(struct lmb *lmb)
453 {
454 	u64 start, size;
455 	char bootm_low[32];
456 	char bootm_mapsize[32];
457 	int i;
458 
459 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
460 		if (!gd->bd->bi_dram[i].size)
461 			break;
462 	}
463 
464 	start = gd->bd->bi_dram[i - 1].start;
465 	size = gd->bd->bi_dram[i - 1].size;
466 
467 	/*
468 	 * 32-bit kernel: ramdisk/fdt shouldn't be loaded to highmem area(768MB+),
469 	 * otherwise "Unable to handle kernel paging request at virtual address ...".
470 	 *
471 	 * So that we hope limit highest address at 768M, but there comes the the
472 	 * problem: ramdisk is a compressed image and it expands after descompress,
473 	 * so it accesses 768MB+ and brings the above "Unable to handle kernel ...".
474 	 *
475 	 * We make a appointment that the highest memory address is 512MB, it
476 	 * makes lmb alloc safer.
477 	 */
478 #ifndef CONFIG_ARM64
479 	if (start >= ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) {
480 		start = gd->bd->bi_dram[i - 2].start;
481 		size = gd->bd->bi_dram[i - 2].size;
482 	}
483 
484 	if ((start + size) > ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M))
485 		size = (u64)CONFIG_SYS_SDRAM_BASE + SZ_512M - start;
486 #endif
487 	sprintf(bootm_low, "0x%llx", start);
488 	sprintf(bootm_mapsize, "0x%llx", size);
489 	env_set("bootm_low", bootm_low);
490 	env_set("bootm_mapsize", bootm_mapsize);
491 }
492 #endif
493 
494 #ifdef CONFIG_BIDRAM
495 int board_bidram_reserve(struct bidram *bidram)
496 {
497 	struct memblock mem;
498 	int ret;
499 
500 	/* ATF */
501 	mem = param_parse_atf_mem();
502 	ret = bidram_reserve(MEMBLK_ID_ATF, mem.base, mem.size);
503 	if (ret)
504 		return ret;
505 
506 	/* PSTORE/ATAGS/SHM */
507 	mem = param_parse_common_resv_mem();
508 	ret = bidram_reserve(MEMBLK_ID_SHM, mem.base, mem.size);
509 	if (ret)
510 		return ret;
511 
512 	/* OP-TEE */
513 	mem = param_parse_optee_mem();
514 	ret = bidram_reserve(MEMBLK_ID_OPTEE, mem.base, mem.size);
515 	if (ret)
516 		return ret;
517 
518 	return 0;
519 }
520 
521 parse_fn_t board_bidram_parse_fn(void)
522 {
523 	return param_parse_ddr_mem;
524 }
525 #endif
526 
527 #ifdef CONFIG_ROCKCHIP_AMP
528 void cpu_secondary_init_r(void)
529 {
530 	amp_cpus_on();
531 }
532 #endif
533 
534 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \
535     defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS)
536 int board_init_f_init_serial(void)
537 {
538 	struct tag *t = atags_get_tag(ATAG_SERIAL);
539 
540 	if (t) {
541 		gd->serial.using_pre_serial = t->u.serial.enable;
542 		gd->serial.addr = t->u.serial.addr;
543 		gd->serial.baudrate = t->u.serial.baudrate;
544 		gd->serial.id = t->u.serial.id;
545 
546 		debug("%s: enable=%d, addr=0x%lx, baudrate=%d, id=%d\n",
547 		      __func__, gd->serial.using_pre_serial,
548 		      gd->serial.addr, gd->serial.baudrate,
549 		      gd->serial.id);
550 	}
551 
552 	return 0;
553 }
554 #endif
555 
556 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
557 #include <fdt_support.h>
558 #include <usb.h>
559 #include <usb/dwc2_udc.h>
560 
561 static struct dwc2_plat_otg_data otg_data = {
562 	.rx_fifo_sz	= 512,
563 	.np_tx_fifo_sz	= 16,
564 	.tx_fifo_sz	= 128,
565 };
566 
567 int board_usb_init(int index, enum usb_init_type init)
568 {
569 	int node;
570 	fdt_addr_t addr;
571 	const fdt32_t *reg;
572 	const void *blob = gd->fdt_blob;
573 
574 	/* find the usb_otg node */
575 	node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2");
576 
577 retry:
578 	if (node > 0) {
579 		reg = fdt_getprop(blob, node, "reg", NULL);
580 		if (!reg)
581 			return -EINVAL;
582 
583 		addr = fdt_translate_address(blob, node, reg);
584 		if (addr == OF_BAD_ADDR) {
585 			pr_err("Not found usb_otg address\n");
586 			return -EINVAL;
587 		}
588 
589 #if defined(CONFIG_ROCKCHIP_RK3288)
590 		if (addr != 0xff580000) {
591 			node = fdt_node_offset_by_compatible(blob, node,
592 							     "snps,dwc2");
593 			goto retry;
594 		}
595 #endif
596 	} else {
597 		/*
598 		 * With kernel dtb support, rk3288 dwc2 otg node
599 		 * use the rockchip legacy dwc2 driver "dwc_otg_310"
600 		 * with the compatible "rockchip,rk3288_usb20_otg",
601 		 * and rk3368 also use the "dwc_otg_310" driver with
602 		 * the compatible "rockchip,rk3368-usb".
603 		 */
604 #if defined(CONFIG_ROCKCHIP_RK3288)
605 		node = fdt_node_offset_by_compatible(blob, -1,
606 				"rockchip,rk3288_usb20_otg");
607 #elif defined(CONFIG_ROCKCHIP_RK3368)
608 		node = fdt_node_offset_by_compatible(blob, -1,
609 				"rockchip,rk3368-usb");
610 #endif
611 		if (node > 0) {
612 			goto retry;
613 		} else {
614 			pr_err("Not found usb_otg device\n");
615 			return -ENODEV;
616 		}
617 	}
618 
619 	otg_data.regs_otg = (uintptr_t)addr;
620 
621 	return dwc2_udc_probe(&otg_data);
622 }
623 
624 int board_usb_cleanup(int index, enum usb_init_type init)
625 {
626 	return 0;
627 }
628 #endif
629