1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <amp.h> 8 #include <clk.h> 9 #include <bidram.h> 10 #include <dm.h> 11 #include <debug_uart.h> 12 #include <key.h> 13 #include <memblk.h> 14 #include <ram.h> 15 #include <syscon.h> 16 #include <sysmem.h> 17 #include <asm/io.h> 18 #include <asm/arch/vendor.h> 19 #include <misc.h> 20 #include <asm/gpio.h> 21 #include <dm/uclass-internal.h> 22 #include <asm/arch/clock.h> 23 #include <asm/arch/cpu.h> 24 #include <asm/arch/periph.h> 25 #include <asm/arch/boot_mode.h> 26 #include <asm/arch/hotkey.h> 27 #include <asm/arch/rk_atags.h> 28 #include <asm/arch/param.h> 29 #ifdef CONFIG_DM_CHARGE_DISPLAY 30 #include <power/charge_display.h> 31 #endif 32 #ifdef CONFIG_DM_DVFS 33 #include <dvfs.h> 34 #endif 35 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN 36 #include <io-domain.h> 37 #endif 38 #ifdef CONFIG_DM_REGULATOR 39 #include <power/regulator.h> 40 #endif 41 #ifdef CONFIG_DRM_ROCKCHIP 42 #include <video_rockchip.h> 43 #endif 44 #ifdef CONFIG_ROCKCHIP_DEBUGGER 45 #include <rockchip_debugger.h> 46 #endif 47 #include <of_live.h> 48 #include <dm/root.h> 49 #include <console.h> 50 51 DECLARE_GLOBAL_DATA_PTR; 52 /* define serialno max length, the max length is 512 Bytes 53 * The remaining bytes are used to ensure that the first 512 bytes 54 * are valid when executing 'env_set("serial#", value)'. 55 */ 56 #define VENDOR_SN_MAX 513 57 #define CPUID_LEN 0x10 58 #define CPUID_OFF 0x7 59 60 static int rockchip_set_ethaddr(void) 61 { 62 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 63 int ret; 64 u8 ethaddr[ARP_HLEN]; 65 char buf[ARP_HLEN_ASCII + 1]; 66 67 ret = vendor_storage_read(VENDOR_LAN_MAC_ID, ethaddr, sizeof(ethaddr)); 68 if (ret > 0 && is_valid_ethaddr(ethaddr)) { 69 sprintf(buf, "%pM", ethaddr); 70 env_set("ethaddr", buf); 71 } 72 #endif 73 return 0; 74 } 75 76 static int rockchip_set_serialno(void) 77 { 78 char serialno_str[VENDOR_SN_MAX]; 79 int ret = 0, i; 80 u8 cpuid[CPUID_LEN] = {0}; 81 u8 low[CPUID_LEN / 2], high[CPUID_LEN / 2]; 82 u64 serialno; 83 84 /* Read serial number from vendor storage part */ 85 memset(serialno_str, 0, VENDOR_SN_MAX); 86 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 87 ret = vendor_storage_read(VENDOR_SN_ID, serialno_str, (VENDOR_SN_MAX-1)); 88 if (ret > 0) { 89 env_set("serial#", serialno_str); 90 } else { 91 #endif 92 #ifdef CONFIG_ROCKCHIP_EFUSE 93 struct udevice *dev; 94 95 /* retrieve the device */ 96 ret = uclass_get_device_by_driver(UCLASS_MISC, 97 DM_GET_DRIVER(rockchip_efuse), &dev); 98 if (ret) { 99 printf("%s: could not find efuse device\n", __func__); 100 return ret; 101 } 102 /* read the cpu_id range from the efuses */ 103 ret = misc_read(dev, CPUID_OFF, &cpuid, sizeof(cpuid)); 104 if (ret) { 105 printf("%s: reading cpuid from the efuses failed\n", __func__); 106 return ret; 107 } 108 #else 109 /* generate random cpuid */ 110 for (i = 0; i < CPUID_LEN; i++) { 111 cpuid[i] = (u8)(rand()); 112 } 113 #endif 114 /* Generate the serial number based on CPU ID */ 115 for (i = 0; i < 8; i++) { 116 low[i] = cpuid[1 + (i << 1)]; 117 high[i] = cpuid[i << 1]; 118 } 119 serialno = crc32_no_comp(0, low, 8); 120 serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; 121 snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno); 122 123 env_set("serial#", serialno_str); 124 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 125 } 126 #endif 127 return ret; 128 } 129 130 #if defined(CONFIG_USB_FUNCTION_FASTBOOT) 131 int fb_set_reboot_flag(void) 132 { 133 printf("Setting reboot to fastboot flag ...\n"); 134 /* Set boot mode to fastboot */ 135 writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG); 136 137 return 0; 138 } 139 #endif 140 141 __weak int rk_board_init(void) 142 { 143 return 0; 144 } 145 146 __weak int rk_board_late_init(void) 147 { 148 return 0; 149 } 150 151 __weak int soc_clk_dump(void) 152 { 153 return 0; 154 } 155 156 __weak int set_armclk_rate(void) 157 { 158 return 0; 159 } 160 161 int board_late_init(void) 162 { 163 rockchip_set_ethaddr(); 164 rockchip_set_serialno(); 165 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 166 setup_boot_mode(); 167 #endif 168 169 #ifdef CONFIG_DM_CHARGE_DISPLAY 170 charge_display(); 171 #endif 172 173 #ifdef CONFIG_DRM_ROCKCHIP 174 rockchip_show_logo(); 175 #endif 176 177 soc_clk_dump(); 178 179 return rk_board_late_init(); 180 } 181 182 #ifdef CONFIG_USING_KERNEL_DTB 183 #include <asm/arch/resource_img.h> 184 185 /* Here, only fixup cru phandle, pmucru is not included */ 186 static int phandles_fixup(void *fdt) 187 { 188 const char *props[] = { "clocks", "assigned-clocks" }; 189 struct udevice *dev; 190 struct uclass *uc; 191 const char *comp; 192 u32 id, nclocks; 193 u32 *clocks; 194 int phandle, ncells; 195 int off, offset; 196 int ret, length; 197 int i, j; 198 int first_phandle = -1; 199 200 phandle = -ENODATA; 201 ncells = -ENODATA; 202 203 /* fdt points to kernel dtb, getting cru phandle and "#clock-cells" */ 204 for (offset = fdt_next_node(fdt, 0, NULL); 205 offset >= 0; 206 offset = fdt_next_node(fdt, offset, NULL)) { 207 comp = fdt_getprop(fdt, offset, "compatible", NULL); 208 if (!comp) 209 continue; 210 211 /* Actually, this is not a good method to get cru node */ 212 off = strlen(comp) - strlen("-cru"); 213 if (off > 0 && !strncmp(comp + off, "-cru", 4)) { 214 phandle = fdt_get_phandle(fdt, offset); 215 ncells = fdtdec_get_int(fdt, offset, 216 "#clock-cells", -ENODATA); 217 break; 218 } 219 } 220 221 if (phandle == -ENODATA || ncells == -ENODATA) 222 return 0; 223 224 debug("%s: target cru: clock-cells:%d, phandle:0x%x\n", 225 __func__, ncells, fdt32_to_cpu(phandle)); 226 227 /* Try to fixup all cru phandle from U-Boot dtb nodes */ 228 for (id = 0; id < UCLASS_COUNT; id++) { 229 ret = uclass_get(id, &uc); 230 if (ret) 231 continue; 232 233 if (list_empty(&uc->dev_head)) 234 continue; 235 236 list_for_each_entry(dev, &uc->dev_head, uclass_node) { 237 /* Only U-Boot node go further */ 238 if (!dev_read_bool(dev, "u-boot,dm-pre-reloc")) 239 continue; 240 241 for (i = 0; i < ARRAY_SIZE(props); i++) { 242 if (!dev_read_prop(dev, props[i], &length)) 243 continue; 244 245 clocks = malloc(length); 246 if (!clocks) 247 return -ENOMEM; 248 249 /* Read "props[]" which contains cru phandle */ 250 nclocks = length / sizeof(u32); 251 if (dev_read_u32_array(dev, props[i], 252 clocks, nclocks)) { 253 free(clocks); 254 continue; 255 } 256 257 /* Fixup with kernel cru phandle */ 258 for (j = 0; j < nclocks; j += (ncells + 1)) { 259 /* 260 * Check: update pmucru phandle with cru 261 * phandle by mistake. 262 */ 263 if (first_phandle == -1) 264 first_phandle = clocks[j]; 265 266 if (clocks[j] != first_phandle) { 267 debug("WARN: %s: first cru phandle=%d, this=%d\n", 268 dev_read_name(dev), 269 first_phandle, clocks[j]); 270 continue; 271 } 272 273 clocks[j] = phandle; 274 } 275 276 /* 277 * Override live dt nodes but not fdt nodes, 278 * because all U-Boot nodes has been imported 279 * to live dt nodes, should use "dev_xxx()". 280 */ 281 dev_write_u32_array(dev, props[i], 282 clocks, nclocks); 283 free(clocks); 284 } 285 } 286 } 287 288 return 0; 289 } 290 291 int init_kernel_dtb(void) 292 { 293 int ret = 0; 294 ulong fdt_addr = 0; 295 296 fdt_addr = env_get_ulong("fdt_addr_r", 16, 0); 297 if (!fdt_addr) { 298 printf("No Found FDT Load Address.\n"); 299 return -1; 300 } 301 302 ret = rockchip_read_dtb_file((void *)fdt_addr); 303 if (ret < 0) { 304 printf("%s dtb in resource read fail\n", __func__); 305 return 0; 306 } 307 308 /* 309 * There is a phandle miss match between U-Boot and kernel dtb node, 310 * the typical is cru phandle, we fixup it in U-Boot live dt nodes. 311 */ 312 phandles_fixup((void *)fdt_addr); 313 314 of_live_build((void *)fdt_addr, (struct device_node **)&gd->of_root); 315 316 dm_scan_fdt((void *)fdt_addr, false); 317 318 gd->fdt_blob = (void *)fdt_addr; 319 320 /* Reserve 'reserved-memory' */ 321 ret = boot_fdt_add_sysmem_rsv_regions((void *)gd->fdt_blob); 322 if (ret) 323 return ret; 324 325 return 0; 326 } 327 #endif 328 329 void board_env_fixup(void) 330 { 331 struct memblock mem; 332 ulong u_addr_r; 333 phys_size_t end; 334 char *addr_r; 335 336 #ifdef ENV_MEM_LAYOUT_SETTINGS1 337 const char *env_addr0[] = { 338 "scriptaddr", "pxefile_addr_r", 339 "fdt_addr_r", "kernel_addr_r", "ramdisk_addr_r", 340 }; 341 const char *env_addr1[] = { 342 "scriptaddr1", "pxefile_addr1_r", 343 "fdt_addr1_r", "kernel_addr1_r", "ramdisk_addr1_r", 344 }; 345 int i; 346 347 /* 128M is a typical ram size for most platform, so as default here */ 348 if (gd->ram_size <= SZ_128M) { 349 /* Replace orignal xxx_addr_r */ 350 for (i = 0; i < ARRAY_SIZE(env_addr1); i++) { 351 addr_r = env_get(env_addr1[i]); 352 if (addr_r) 353 env_set(env_addr0[i], addr_r); 354 } 355 } 356 #endif 357 /* If bl32 is disabled, maybe kernel can be load to lower address. */ 358 if (!(gd->flags & GD_FLG_BL32_ENABLED)) { 359 addr_r = env_get("kernel_addr_no_bl32_r"); 360 if (addr_r) 361 env_set("kernel_addr_r", addr_r); 362 /* If bl32 is enlarged, we move ramdisk addr right behind it */ 363 } else { 364 mem = param_parse_optee_mem(); 365 end = mem.base + mem.size; 366 u_addr_r = env_get_ulong("ramdisk_addr_r", 16, 0); 367 if (u_addr_r >= mem.base && u_addr_r < end) 368 env_set_hex("ramdisk_addr_r", end); 369 } 370 } 371 372 static void early_download_init(void) 373 { 374 #if defined(CONFIG_PWRKEY_DNL_TRIGGER_NUM) && \ 375 (CONFIG_PWRKEY_DNL_TRIGGER_NUM > 0) 376 if (pwrkey_download_init()) 377 printf("Pwrkey download init failed\n"); 378 #endif 379 380 if (!tstc()) 381 return; 382 383 gd->console_evt = getc(); 384 if (gd->console_evt <= 0x1a) /* 'z' */ 385 printf("Hotkey: ctrl+%c\n", (gd->console_evt + 'a' - 1)); 386 387 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 388 /* ctrl+b */ 389 if (is_hotkey(HK_BROM_DNL)) { 390 printf("Enter bootrom download..."); 391 flushc(); 392 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 393 do_reset(NULL, 0, 0, NULL); 394 printf("failed!\n"); 395 } 396 #endif 397 } 398 399 int board_init(void) 400 { 401 int ret; 402 403 board_debug_uart_init(); 404 405 #ifdef CONFIG_USING_KERNEL_DTB 406 init_kernel_dtb(); 407 #endif 408 early_download_init(); 409 410 /* 411 * pmucru isn't referenced on some platforms, so pmucru driver can't 412 * probe that the "assigned-clocks" is unused. 413 */ 414 clks_probe(); 415 #ifdef CONFIG_DM_REGULATOR 416 ret = regulators_enable_boot_on(false); 417 if (ret) 418 debug("%s: Cannot enable boot on regulator\n", __func__); 419 #endif 420 421 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN 422 io_domain_init(); 423 #endif 424 425 set_armclk_rate(); 426 427 #ifdef CONFIG_DM_DVFS 428 dvfs_init(true); 429 #endif 430 431 return rk_board_init(); 432 } 433 434 int interrupt_debugger_init(void) 435 { 436 int ret = 0; 437 438 #ifdef CONFIG_ROCKCHIP_DEBUGGER 439 ret = rockchip_debugger_init(); 440 #endif 441 return ret; 442 } 443 444 #if defined(CONFIG_ROCKCHIP_RK1808) && !defined(CONFIG_COPROCESSOR_RK1808) 445 #define PINCTRL_EMMC_BUS8_PATH "/pinctrl/emmc/emmc-bus8" 446 #define PINCTRL_EMMC_CMD_PATH "/pinctrl/emmc/emmc-cmd" 447 #define PINCTRL_EMMC_CLK_PATH "/pinctrl/emmc/emmc-clk" 448 #define PINCTRL_PCFG_PU_2MA_PATH "/pinctrl/pcfg-pull-up-2ma" 449 #define MAX_ROCKCHIP_PINS_ENTRIES 12 450 451 static int rockchip_pinctrl_cfg_fdt_fixup(const char *path, u32 new_phandle) 452 { 453 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 454 const u32 *data; 455 int i, count; 456 int node; 457 458 node = fdt_path_offset(gd->fdt_blob, path); 459 if (node < 0) { 460 debug("%s: can't find: %s\n", __func__, path); 461 return node; 462 } 463 464 data = fdt_getprop(gd->fdt_blob, node, "rockchip,pins", &count); 465 if (!data) { 466 debug("%s: can't find prop \"rockchip,pins\"\n", __func__); 467 return -ENODATA; 468 } 469 470 count /= sizeof(u32); 471 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 472 debug("%s: %d is over max count\n", __func__, count); 473 return -EINVAL; 474 } 475 476 for (i = 0; i < count; i++) 477 cells[i] = data[i]; 478 479 for (i = 0; i < (count >> 2); i++) 480 cells[4 * i + 3] = cpu_to_fdt32(new_phandle); 481 482 fdt_setprop((void *)gd->fdt_blob, node, "rockchip,pins", 483 &cells, count * sizeof(u32)); 484 485 return 0; 486 } 487 #endif 488 489 int board_fdt_fixup(void *blob) 490 { 491 int ret = 0; 492 493 /* 494 * Common fixup for DRM 495 */ 496 #ifdef CONFIG_DRM_ROCKCHIP 497 rockchip_display_fixup(blob); 498 #endif 499 500 /* 501 * Platform fixup: 502 * 503 * - RK3288: Recognize RK3288W by HDMI Revision ID is 0x1A; 504 * - RK1808: MMC strength 2mA; 505 */ 506 #ifdef CONFIG_ROCKCHIP_RK3288 507 if (soc_is_rk3288w()) { 508 ret = fdt_setprop_string(blob, 0, 509 "compatible", "rockchip,rk3288w"); 510 if (ret) 511 printf("fdt set compatible failed: %d\n", ret); 512 } 513 #elif defined(CONFIG_ROCKCHIP_RK1808) && !defined(CONFIG_COPROCESSOR_RK1808) 514 struct tag *t; 515 u32 ph_pu_2ma; 516 517 t = atags_get_tag(ATAG_SOC_INFO); 518 if (!t) 519 return 0; 520 521 debug("soc=0x%x, flags=0x%x\n", t->u.soc.name, t->u.soc.flags); 522 523 if (t->u.soc.flags != SOC_FLAGS_ET00) 524 return 0; 525 526 ph_pu_2ma = fdt_get_phandle(gd->fdt_blob, 527 fdt_path_offset(gd->fdt_blob, PINCTRL_PCFG_PU_2MA_PATH)); 528 if (!ph_pu_2ma) { 529 debug("Can't find: %s\n", PINCTRL_PCFG_PU_2MA_PATH); 530 return -EINVAL; 531 } 532 533 ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_BUS8_PATH, ph_pu_2ma); 534 ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_CMD_PATH, ph_pu_2ma); 535 ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_CLK_PATH, ph_pu_2ma); 536 #endif 537 538 return ret; 539 } 540 541 #ifdef CONFIG_ARM64_BOOT_AARCH32 542 /* 543 * Fixup MMU region attr for OP-TEE on ARMv8 CPU: 544 * 545 * What ever U-Boot is 64-bit or 32-bit mode, the OP-TEE is always 64-bit mode. 546 * 547 * Command for OP-TEE: 548 * 64-bit mode: dcache is always enabled; 549 * 32-bit mode: dcache is always disabled(Due to some unknown issue); 550 * 551 * Command for U-Boot: 552 * 64-bit mode: MMU table is static defined in rkxxx.c file, all memory 553 * regions are mapped. That's good to match OP-TEE MMU policy. 554 * 555 * 32-bit mode: MMU table is setup according to gd->bd->bi_dram[..] where 556 * the OP-TEE region has been reserved, so it can not be 557 * mapped(i.e. dcache is disabled). That's also good to match 558 * OP-TEE MMU policy. 559 * 560 * For the data coherence when communication between U-Boot and OP-TEE, U-Boot 561 * should follow OP-TEE MMU policy. 562 * 563 * Here is the special: 564 * When CONFIG_ARM64_BOOT_AARCH32 is enabled, U-Boot is 32-bit mode while 565 * OP-TEE is still 64-bit mode. U-Boot would not map MMU table for OP-TEE 566 * region(but OP-TEE requires it cacheable) so we fixup here. 567 */ 568 int board_initr_caches_fixup(void) 569 { 570 struct memblock mem; 571 572 mem = param_parse_optee_mem(); 573 if (mem.size) 574 mmu_set_region_dcache_behaviour(mem.base, mem.size, 575 DCACHE_WRITEBACK); 576 return 0; 577 } 578 #endif 579 580 void board_quiesce_devices(void) 581 { 582 hotkey_run(HK_CMDLINE); 583 hotkey_run(HK_CLI); 584 585 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 586 /* Destroy atags makes next warm boot safer */ 587 atags_destroy(); 588 #endif 589 590 #if defined(CONFIG_CONSOLE_RECORD) 591 /* Print record console data */ 592 console_record_print_purge(); 593 #endif 594 } 595 596 void enable_caches(void) 597 { 598 icache_enable(); 599 dcache_enable(); 600 } 601 602 #ifdef CONFIG_LMB 603 /* 604 * Using last bi_dram[...] to initialize "bootm_low" and "bootm_mapsize". 605 * This makes lmb_alloc_base() always alloc from tail of sdram. 606 * If we don't assign it, bi_dram[0] is used by default and it may cause 607 * lmb_alloc_base() fail when bi_dram[0] range is small. 608 */ 609 void board_lmb_reserve(struct lmb *lmb) 610 { 611 u64 start, size; 612 char bootm_low[32]; 613 char bootm_mapsize[32]; 614 int i; 615 616 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 617 if (!gd->bd->bi_dram[i].size) 618 break; 619 } 620 621 start = gd->bd->bi_dram[i - 1].start; 622 size = gd->bd->bi_dram[i - 1].size; 623 624 /* 625 * 32-bit kernel: ramdisk/fdt shouldn't be loaded to highmem area(768MB+), 626 * otherwise "Unable to handle kernel paging request at virtual address ...". 627 * 628 * So that we hope limit highest address at 768M, but there comes the the 629 * problem: ramdisk is a compressed image and it expands after descompress, 630 * so it accesses 768MB+ and brings the above "Unable to handle kernel ...". 631 * 632 * We make a appointment that the highest memory address is 512MB, it 633 * makes lmb alloc safer. 634 */ 635 #ifndef CONFIG_ARM64 636 if (start >= ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) { 637 start = gd->bd->bi_dram[i - 2].start; 638 size = gd->bd->bi_dram[i - 2].size; 639 } 640 641 if ((start + size) > ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) 642 size = (u64)CONFIG_SYS_SDRAM_BASE + SZ_512M - start; 643 #endif 644 sprintf(bootm_low, "0x%llx", start); 645 sprintf(bootm_mapsize, "0x%llx", size); 646 env_set("bootm_low", bootm_low); 647 env_set("bootm_mapsize", bootm_mapsize); 648 } 649 #endif 650 651 #ifdef CONFIG_BIDRAM 652 int board_bidram_reserve(struct bidram *bidram) 653 { 654 struct memblock mem; 655 int ret; 656 657 /* ATF */ 658 mem = param_parse_atf_mem(); 659 ret = bidram_reserve(MEMBLK_ID_ATF, mem.base, mem.size); 660 if (ret) 661 return ret; 662 663 /* PSTORE/ATAGS/SHM */ 664 mem = param_parse_common_resv_mem(); 665 ret = bidram_reserve(MEMBLK_ID_SHM, mem.base, mem.size); 666 if (ret) 667 return ret; 668 669 /* OP-TEE */ 670 mem = param_parse_optee_mem(); 671 ret = bidram_reserve(MEMBLK_ID_OPTEE, mem.base, mem.size); 672 if (ret) 673 return ret; 674 675 return 0; 676 } 677 678 parse_fn_t board_bidram_parse_fn(void) 679 { 680 return param_parse_ddr_mem; 681 } 682 #endif 683 684 #ifdef CONFIG_ROCKCHIP_AMP 685 void cpu_secondary_init_r(void) 686 { 687 amp_cpus_on(); 688 } 689 #endif 690 691 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \ 692 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS) 693 int board_init_f_init_serial(void) 694 { 695 struct tag *t = atags_get_tag(ATAG_SERIAL); 696 697 if (t) { 698 gd->serial.using_pre_serial = t->u.serial.enable; 699 gd->serial.addr = t->u.serial.addr; 700 gd->serial.baudrate = t->u.serial.baudrate; 701 gd->serial.id = t->u.serial.id; 702 703 debug("%s: enable=%d, addr=0x%lx, baudrate=%d, id=%d\n", 704 __func__, gd->serial.using_pre_serial, 705 gd->serial.addr, gd->serial.baudrate, 706 gd->serial.id); 707 } 708 709 return 0; 710 } 711 #endif 712 713 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) 714 #include <fdt_support.h> 715 #include <usb.h> 716 #include <usb/dwc2_udc.h> 717 718 static struct dwc2_plat_otg_data otg_data = { 719 .rx_fifo_sz = 512, 720 .np_tx_fifo_sz = 16, 721 .tx_fifo_sz = 128, 722 }; 723 724 int board_usb_init(int index, enum usb_init_type init) 725 { 726 int node; 727 fdt_addr_t addr; 728 const fdt32_t *reg; 729 const void *blob = gd->fdt_blob; 730 731 /* find the usb_otg node */ 732 node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); 733 734 retry: 735 if (node > 0) { 736 reg = fdt_getprop(blob, node, "reg", NULL); 737 if (!reg) 738 return -EINVAL; 739 740 addr = fdt_translate_address(blob, node, reg); 741 if (addr == OF_BAD_ADDR) { 742 pr_err("Not found usb_otg address\n"); 743 return -EINVAL; 744 } 745 746 #if defined(CONFIG_ROCKCHIP_RK3288) 747 if (addr != 0xff580000) { 748 node = fdt_node_offset_by_compatible(blob, node, 749 "snps,dwc2"); 750 goto retry; 751 } 752 #endif 753 } else { 754 /* 755 * With kernel dtb support, rk3288 dwc2 otg node 756 * use the rockchip legacy dwc2 driver "dwc_otg_310" 757 * with the compatible "rockchip,rk3288_usb20_otg", 758 * and rk3368 also use the "dwc_otg_310" driver with 759 * the compatible "rockchip,rk3368-usb". 760 */ 761 #if defined(CONFIG_ROCKCHIP_RK3288) 762 node = fdt_node_offset_by_compatible(blob, -1, 763 "rockchip,rk3288_usb20_otg"); 764 #elif defined(CONFIG_ROCKCHIP_RK3368) 765 node = fdt_node_offset_by_compatible(blob, -1, 766 "rockchip,rk3368-usb"); 767 #endif 768 if (node > 0) { 769 goto retry; 770 } else { 771 pr_err("Not found usb_otg device\n"); 772 return -ENODEV; 773 } 774 } 775 776 otg_data.regs_otg = (uintptr_t)addr; 777 778 return dwc2_udc_probe(&otg_data); 779 } 780 781 int board_usb_cleanup(int index, enum usb_init_type init) 782 { 783 return 0; 784 } 785 #endif 786