1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <ram.h> 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 int board_init(void) 17 { 18 return 0; 19 } 20 21 int dram_init(void) 22 { 23 struct ram_info ram; 24 struct udevice *dev; 25 int ret; 26 27 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 28 if (ret) { 29 debug("DRAM init failed: %d\n", ret); 30 return ret; 31 } 32 ret = ram_get_info(dev, &ram); 33 if (ret) { 34 debug("Cannot get DRAM size: %d\n", ret); 35 return ret; 36 } 37 debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size); 38 gd->ram_size = ram.size; 39 40 return 0; 41 } 42 43 #ifndef CONFIG_SYS_DCACHE_OFF 44 void enable_caches(void) 45 { 46 /* Enable D-cache. I-cache is already enabled in start.S */ 47 dcache_enable(); 48 } 49 #endif 50 51 void lowlevel_init(void) 52 { 53 } 54 55 static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc, 56 char * const argv[]) 57 { 58 static const struct { 59 char *name; 60 int id; 61 } clks[] = { 62 { "osc", CLK_OSC }, 63 { "apll", CLK_ARM }, 64 { "dpll", CLK_DDR }, 65 { "cpll", CLK_CODEC }, 66 { "gpll", CLK_GENERAL }, 67 #ifdef CONFIG_ROCKCHIP_RK3036 68 { "mpll", CLK_NEW }, 69 #else 70 { "npll", CLK_NEW }, 71 #endif 72 }; 73 int ret, i; 74 struct udevice *dev; 75 76 ret = uclass_get_device(UCLASS_CLK, 0, &dev); 77 if (ret) { 78 printf("clk-uclass not found\n"); 79 return 0; 80 } 81 82 for (i = 0; i < ARRAY_SIZE(clks); i++) { 83 struct clk clk; 84 ulong rate; 85 86 clk.id = clks[i].id; 87 ret = clk_request(dev, &clk); 88 if (ret < 0) 89 continue; 90 91 rate = clk_get_rate(&clk); 92 printf("%s: %lu\n", clks[i].name, rate); 93 94 clk_free(&clk); 95 } 96 97 return 0; 98 } 99 100 U_BOOT_CMD( 101 clock, 2, 1, do_clock, 102 "display information about clocks", 103 "" 104 ); 105