1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <clk.h> 8 #include <dm.h> 9 #include <debug_uart.h> 10 #include <ram.h> 11 #include <syscon.h> 12 #include <sysmem.h> 13 #include <asm/io.h> 14 #include <asm/arch/vendor.h> 15 #include <misc.h> 16 #include <asm/gpio.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/periph.h> 19 #include <asm/arch/boot_mode.h> 20 #include <asm/arch/rk_atags.h> 21 #include <asm/arch/param.h> 22 #ifdef CONFIG_DM_CHARGE_DISPLAY 23 #include <power/charge_display.h> 24 #endif 25 #ifdef CONFIG_DM_DVFS 26 #include <dvfs.h> 27 #endif 28 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN 29 #include <io-domain.h> 30 #endif 31 #ifdef CONFIG_DM_REGULATOR 32 #include <power/regulator.h> 33 #endif 34 #ifdef CONFIG_DRM_ROCKCHIP 35 #include <video_rockchip.h> 36 #endif 37 #ifdef CONFIG_ROCKCHIP_DEBUGGER 38 #include <rockchip_debugger.h> 39 #endif 40 #include <of_live.h> 41 #include <dm/root.h> 42 #include <console.h> 43 44 DECLARE_GLOBAL_DATA_PTR; 45 /* define serialno max length, the max length is 512 Bytes 46 * The remaining bytes are used to ensure that the first 512 bytes 47 * are valid when executing 'env_set("serial#", value)'. 48 */ 49 #define VENDOR_SN_MAX 513 50 #define CPUID_LEN 0x10 51 #define CPUID_OFF 0x7 52 53 static int rockchip_set_serialno(void) 54 { 55 char serialno_str[VENDOR_SN_MAX]; 56 int ret = 0, i; 57 u8 cpuid[CPUID_LEN] = {0}; 58 u8 low[CPUID_LEN / 2], high[CPUID_LEN / 2]; 59 u64 serialno; 60 61 /* Read serial number from vendor storage part */ 62 memset(serialno_str, 0, VENDOR_SN_MAX); 63 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 64 ret = vendor_storage_read(VENDOR_SN_ID, serialno_str, (VENDOR_SN_MAX-1)); 65 if (ret > 0) { 66 env_set("serial#", serialno_str); 67 } else { 68 #endif 69 #ifdef CONFIG_ROCKCHIP_EFUSE 70 struct udevice *dev; 71 72 /* retrieve the device */ 73 ret = uclass_get_device_by_driver(UCLASS_MISC, 74 DM_GET_DRIVER(rockchip_efuse), &dev); 75 if (ret) { 76 printf("%s: could not find efuse device\n", __func__); 77 return ret; 78 } 79 /* read the cpu_id range from the efuses */ 80 ret = misc_read(dev, CPUID_OFF, &cpuid, sizeof(cpuid)); 81 if (ret) { 82 printf("%s: reading cpuid from the efuses failed\n", __func__); 83 return ret; 84 } 85 #else 86 /* generate random cpuid */ 87 for (i = 0; i < CPUID_LEN; i++) { 88 cpuid[i] = (u8)(rand()); 89 } 90 #endif 91 /* Generate the serial number based on CPU ID */ 92 for (i = 0; i < 8; i++) { 93 low[i] = cpuid[1 + (i << 1)]; 94 high[i] = cpuid[i << 1]; 95 } 96 serialno = crc32_no_comp(0, low, 8); 97 serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; 98 snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno); 99 100 env_set("serial#", serialno_str); 101 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 102 } 103 #endif 104 return ret; 105 } 106 107 #if defined(CONFIG_USB_FUNCTION_FASTBOOT) 108 int fb_set_reboot_flag(void) 109 { 110 printf("Setting reboot to fastboot flag ...\n"); 111 /* Set boot mode to fastboot */ 112 writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG); 113 114 return 0; 115 } 116 #endif 117 118 __weak int rk_board_init(void) 119 { 120 return 0; 121 } 122 123 __weak int rk_board_late_init(void) 124 { 125 return 0; 126 } 127 128 __weak int soc_clk_dump(void) 129 { 130 return 0; 131 } 132 133 __weak int set_armclk_rate(void) 134 { 135 return 0; 136 } 137 138 int board_late_init(void) 139 { 140 rockchip_set_serialno(); 141 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 142 setup_boot_mode(); 143 #endif 144 145 #ifdef CONFIG_DM_CHARGE_DISPLAY 146 charge_display(); 147 #endif 148 149 #ifdef CONFIG_DRM_ROCKCHIP 150 rockchip_show_logo(); 151 #endif 152 153 soc_clk_dump(); 154 155 return rk_board_late_init(); 156 } 157 158 #ifdef CONFIG_USING_KERNEL_DTB 159 #include <asm/arch/resource_img.h> 160 161 int init_kernel_dtb(void) 162 { 163 int ret = 0; 164 ulong fdt_addr = 0; 165 166 fdt_addr = env_get_ulong("fdt_addr_r", 16, 0); 167 if (!fdt_addr) { 168 printf("No Found FDT Load Address.\n"); 169 return -1; 170 } 171 172 ret = rockchip_read_dtb_file((void *)fdt_addr); 173 if (ret < 0) { 174 printf("%s dtb in resource read fail\n", __func__); 175 return 0; 176 } 177 178 of_live_build((void *)fdt_addr, (struct device_node **)&gd->of_root); 179 180 dm_scan_fdt((void *)fdt_addr, false); 181 182 gd->fdt_blob = (void *)fdt_addr; 183 184 /* Reserve 'reserved-memory' */ 185 ret = boot_fdt_add_sysmem_rsv_regions((void *)gd->fdt_blob); 186 if (ret) 187 return ret; 188 189 return 0; 190 } 191 #endif 192 193 void board_env_fixup(void) 194 { 195 ulong kernel_addr_r; 196 197 if (gd->flags & GD_FLG_BL32_ENABLED) 198 return; 199 200 /* If bl32 is disabled, maybe kernel can be load to lower address. */ 201 kernel_addr_r = env_get_ulong("kernel_addr_no_bl32_r", 16, -1); 202 if (kernel_addr_r != -1) 203 env_set_hex("kernel_addr_r", kernel_addr_r); 204 } 205 206 static void early_bootrom_download(void) 207 { 208 if (!tstc()) 209 return; 210 211 gd->console_evt = getc(); 212 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 213 /* ctrl+b */ 214 if (gd->console_evt == CONSOLE_EVT_CTRL_B) { 215 printf("Enter bootrom download..."); 216 mdelay(100); 217 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 218 do_reset(NULL, 0, 0, NULL); 219 printf("failed!\n"); 220 } 221 #endif 222 } 223 224 int board_init(void) 225 { 226 int ret; 227 228 board_debug_uart_init(); 229 early_bootrom_download(); 230 231 #ifdef CONFIG_USING_KERNEL_DTB 232 init_kernel_dtb(); 233 #endif 234 /* 235 * pmucru isn't referenced on some platforms, so pmucru driver can't 236 * probe that the "assigned-clocks" is unused. 237 */ 238 clks_probe(); 239 #ifdef CONFIG_DM_REGULATOR 240 ret = regulators_enable_boot_on(false); 241 if (ret) 242 debug("%s: Cannot enable boot on regulator\n", __func__); 243 #endif 244 245 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN 246 io_domain_init(); 247 #endif 248 249 set_armclk_rate(); 250 251 #ifdef CONFIG_DM_DVFS 252 dvfs_init(true); 253 #endif 254 255 return rk_board_init(); 256 } 257 258 int interrupt_debugger_init(void) 259 { 260 int ret = 0; 261 262 #ifdef CONFIG_ROCKCHIP_DEBUGGER 263 ret = rockchip_debugger_init(); 264 #endif 265 return ret; 266 } 267 268 int board_fdt_fixup(void *blob) 269 { 270 __maybe_unused int ret = 0; 271 272 #ifdef CONFIG_DRM_ROCKCHIP 273 rockchip_display_fixup(blob); 274 #endif 275 276 #ifdef CONFIG_ROCKCHIP_RK3288 277 /* RK3288W HDMI Revision ID is 0x1A */ 278 if (readl(0xff980004) == 0x1A) { 279 ret = fdt_setprop_string(blob, 0, 280 "compatible", "rockchip,rk3288w"); 281 if (ret) 282 printf("fdt set compatible failed: %d\n", ret); 283 } 284 #endif 285 286 return ret; 287 } 288 289 void board_quiesce_devices(void) 290 { 291 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 292 /* Destroy atags makes next warm boot safer */ 293 atags_destroy(); 294 #endif 295 } 296 297 void enable_caches(void) 298 { 299 icache_enable(); 300 dcache_enable(); 301 } 302 303 #ifdef CONFIG_LMB 304 /* 305 * Using last bi_dram[...] to initialize "bootm_low" and "bootm_mapsize". 306 * This makes lmb_alloc_base() always alloc from tail of sdram. 307 * If we don't assign it, bi_dram[0] is used by default and it may cause 308 * lmb_alloc_base() fail when bi_dram[0] range is small. 309 */ 310 void board_lmb_reserve(struct lmb *lmb) 311 { 312 u64 start, size; 313 char bootm_low[32]; 314 char bootm_mapsize[32]; 315 int i; 316 317 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 318 if (!gd->bd->bi_dram[i].size) 319 break; 320 } 321 322 start = gd->bd->bi_dram[i - 1].start; 323 size = gd->bd->bi_dram[i - 1].size; 324 325 /* 326 * 32-bit kernel: ramdisk/fdt shouldn't be loaded to highmem area(768MB+), 327 * otherwise "Unable to handle kernel paging request at virtual address ...". 328 * 329 * So that we hope limit highest address at 768M, but there comes the the 330 * problem: ramdisk is a compressed image and it expands after descompress, 331 * so it accesses 768MB+ and brings the above "Unable to handle kernel ...". 332 * 333 * We make a appointment that the highest memory address is 512MB, it 334 * makes lmb alloc safer. 335 */ 336 #ifndef CONFIG_ARM64 337 if (start >= ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) { 338 start = gd->bd->bi_dram[i - 2].start; 339 size = gd->bd->bi_dram[i - 2].size; 340 } 341 342 if ((start + size) > ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) 343 size = (u64)CONFIG_SYS_SDRAM_BASE + SZ_512M - start; 344 #endif 345 sprintf(bootm_low, "0x%llx", start); 346 sprintf(bootm_mapsize, "0x%llx", size); 347 env_set("bootm_low", bootm_low); 348 env_set("bootm_mapsize", bootm_mapsize); 349 } 350 #endif 351 352 #ifdef CONFIG_SYSMEM 353 int board_sysmem_reserve(struct sysmem *sysmem) 354 { 355 struct sysmem_property prop; 356 int ret; 357 358 /* ATF */ 359 prop = param_parse_atf_mem(); 360 ret = sysmem_reserve(prop.name, prop.base, prop.size); 361 if (ret) 362 return ret; 363 364 /* PSTORE/ATAGS/SHM */ 365 prop = param_parse_common_resv_mem(); 366 ret = sysmem_reserve(prop.name, prop.base, prop.size); 367 if (ret) 368 return ret; 369 370 /* OP-TEE */ 371 prop = param_parse_optee_mem(); 372 ret = sysmem_reserve(prop.name, prop.base, prop.size); 373 if (ret) 374 return ret; 375 376 return 0; 377 } 378 #endif 379 380 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \ 381 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS) 382 int board_init_f_init_serial(void) 383 { 384 struct tag *t = atags_get_tag(ATAG_SERIAL); 385 386 if (t) { 387 gd->serial.using_pre_serial = t->u.serial.enable; 388 gd->serial.addr = t->u.serial.addr; 389 gd->serial.baudrate = t->u.serial.baudrate; 390 gd->serial.id = t->u.serial.id; 391 392 debug("%s: enable=%d, addr=0x%lx, baudrate=%d, id=%d\n", 393 __func__, gd->serial.using_pre_serial, 394 gd->serial.addr, gd->serial.baudrate, 395 gd->serial.id); 396 } 397 398 return 0; 399 } 400 #endif 401 402 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) 403 #include <fdt_support.h> 404 #include <usb.h> 405 #include <usb/dwc2_udc.h> 406 407 static struct dwc2_plat_otg_data otg_data = { 408 .rx_fifo_sz = 512, 409 .np_tx_fifo_sz = 16, 410 .tx_fifo_sz = 128, 411 }; 412 413 int board_usb_init(int index, enum usb_init_type init) 414 { 415 int node; 416 fdt_addr_t addr; 417 const fdt32_t *reg; 418 const void *blob = gd->fdt_blob; 419 420 /* find the usb_otg node */ 421 node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); 422 423 retry: 424 if (node > 0) { 425 reg = fdt_getprop(blob, node, "reg", NULL); 426 if (!reg) 427 return -EINVAL; 428 429 addr = fdt_translate_address(blob, node, reg); 430 if (addr == OF_BAD_ADDR) { 431 pr_err("Not found usb_otg address\n"); 432 return -EINVAL; 433 } 434 435 #if defined(CONFIG_ROCKCHIP_RK3288) 436 if (addr != 0xff580000) { 437 node = fdt_node_offset_by_compatible(blob, node, 438 "snps,dwc2"); 439 goto retry; 440 } 441 #endif 442 } else { 443 /* 444 * With kernel dtb support, rk3288 dwc2 otg node 445 * use the rockchip legacy dwc2 driver "dwc_otg_310" 446 * with the compatible "rockchip,rk3288_usb20_otg", 447 * and rk3368 also use the "dwc_otg_310" driver with 448 * the compatible "rockchip,rk3368-usb". 449 */ 450 #if defined(CONFIG_ROCKCHIP_RK3288) 451 node = fdt_node_offset_by_compatible(blob, -1, 452 "rockchip,rk3288_usb20_otg"); 453 #elif defined(CONFIG_ROCKCHIP_RK3368) 454 node = fdt_node_offset_by_compatible(blob, -1, 455 "rockchip,rk3368-usb"); 456 #endif 457 if (node > 0) { 458 goto retry; 459 } else { 460 pr_err("Not found usb_otg device\n"); 461 return -ENODEV; 462 } 463 } 464 465 otg_data.regs_otg = (uintptr_t)addr; 466 467 return dwc2_udc_probe(&otg_data); 468 } 469 470 int board_usb_cleanup(int index, enum usb_init_type init) 471 { 472 return 0; 473 } 474 #endif 475