1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <amp.h> 8 #include <clk.h> 9 #include <bidram.h> 10 #include <dm.h> 11 #include <debug_uart.h> 12 #include <memblk.h> 13 #include <ram.h> 14 #include <syscon.h> 15 #include <sysmem.h> 16 #include <asm/io.h> 17 #include <asm/arch/vendor.h> 18 #include <misc.h> 19 #include <asm/gpio.h> 20 #include <dm/uclass-internal.h> 21 #include <asm/arch/clock.h> 22 #include <asm/arch/cpu.h> 23 #include <asm/arch/periph.h> 24 #include <asm/arch/boot_mode.h> 25 #include <asm/arch/hotkey.h> 26 #include <asm/arch/rk_atags.h> 27 #include <asm/arch/param.h> 28 #ifdef CONFIG_DM_CHARGE_DISPLAY 29 #include <power/charge_display.h> 30 #endif 31 #ifdef CONFIG_DM_DVFS 32 #include <dvfs.h> 33 #endif 34 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN 35 #include <io-domain.h> 36 #endif 37 #ifdef CONFIG_DM_REGULATOR 38 #include <power/regulator.h> 39 #endif 40 #ifdef CONFIG_DRM_ROCKCHIP 41 #include <video_rockchip.h> 42 #endif 43 #ifdef CONFIG_ROCKCHIP_DEBUGGER 44 #include <rockchip_debugger.h> 45 #endif 46 #include <of_live.h> 47 #include <dm/root.h> 48 #include <console.h> 49 50 DECLARE_GLOBAL_DATA_PTR; 51 /* define serialno max length, the max length is 512 Bytes 52 * The remaining bytes are used to ensure that the first 512 bytes 53 * are valid when executing 'env_set("serial#", value)'. 54 */ 55 #define VENDOR_SN_MAX 513 56 #define CPUID_LEN 0x10 57 #define CPUID_OFF 0x7 58 59 static int rockchip_set_ethaddr(void) 60 { 61 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 62 int ret; 63 u8 ethaddr[ARP_HLEN]; 64 char buf[ARP_HLEN_ASCII + 1]; 65 66 ret = vendor_storage_read(VENDOR_LAN_MAC_ID, ethaddr, sizeof(ethaddr)); 67 if (ret > 0 && is_valid_ethaddr(ethaddr)) { 68 sprintf(buf, "%pM", ethaddr); 69 env_set("ethaddr", buf); 70 } 71 #endif 72 return 0; 73 } 74 75 static int rockchip_set_serialno(void) 76 { 77 char serialno_str[VENDOR_SN_MAX]; 78 int ret = 0, i; 79 u8 cpuid[CPUID_LEN] = {0}; 80 u8 low[CPUID_LEN / 2], high[CPUID_LEN / 2]; 81 u64 serialno; 82 83 /* Read serial number from vendor storage part */ 84 memset(serialno_str, 0, VENDOR_SN_MAX); 85 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 86 ret = vendor_storage_read(VENDOR_SN_ID, serialno_str, (VENDOR_SN_MAX-1)); 87 if (ret > 0) { 88 env_set("serial#", serialno_str); 89 } else { 90 #endif 91 #ifdef CONFIG_ROCKCHIP_EFUSE 92 struct udevice *dev; 93 94 /* retrieve the device */ 95 ret = uclass_get_device_by_driver(UCLASS_MISC, 96 DM_GET_DRIVER(rockchip_efuse), &dev); 97 if (ret) { 98 printf("%s: could not find efuse device\n", __func__); 99 return ret; 100 } 101 /* read the cpu_id range from the efuses */ 102 ret = misc_read(dev, CPUID_OFF, &cpuid, sizeof(cpuid)); 103 if (ret) { 104 printf("%s: reading cpuid from the efuses failed\n", __func__); 105 return ret; 106 } 107 #else 108 /* generate random cpuid */ 109 for (i = 0; i < CPUID_LEN; i++) { 110 cpuid[i] = (u8)(rand()); 111 } 112 #endif 113 /* Generate the serial number based on CPU ID */ 114 for (i = 0; i < 8; i++) { 115 low[i] = cpuid[1 + (i << 1)]; 116 high[i] = cpuid[i << 1]; 117 } 118 serialno = crc32_no_comp(0, low, 8); 119 serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; 120 snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno); 121 122 env_set("serial#", serialno_str); 123 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 124 } 125 #endif 126 return ret; 127 } 128 129 #if defined(CONFIG_USB_FUNCTION_FASTBOOT) 130 int fb_set_reboot_flag(void) 131 { 132 printf("Setting reboot to fastboot flag ...\n"); 133 /* Set boot mode to fastboot */ 134 writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG); 135 136 return 0; 137 } 138 #endif 139 140 __weak int rk_board_init(void) 141 { 142 return 0; 143 } 144 145 __weak int rk_board_late_init(void) 146 { 147 return 0; 148 } 149 150 __weak int soc_clk_dump(void) 151 { 152 return 0; 153 } 154 155 __weak int set_armclk_rate(void) 156 { 157 return 0; 158 } 159 160 int board_late_init(void) 161 { 162 rockchip_set_ethaddr(); 163 rockchip_set_serialno(); 164 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 165 setup_boot_mode(); 166 #endif 167 168 #ifdef CONFIG_DM_CHARGE_DISPLAY 169 charge_display(); 170 #endif 171 172 #ifdef CONFIG_DRM_ROCKCHIP 173 rockchip_show_logo(); 174 #endif 175 176 soc_clk_dump(); 177 178 return rk_board_late_init(); 179 } 180 181 #ifdef CONFIG_USING_KERNEL_DTB 182 #include <asm/arch/resource_img.h> 183 184 /* Here, only fixup cru phandle, pmucru is not included */ 185 static int phandles_fixup(void *fdt) 186 { 187 const char *props[] = { "clocks", "assigned-clocks" }; 188 struct udevice *dev; 189 struct uclass *uc; 190 const char *comp; 191 u32 id, nclocks; 192 u32 *clocks; 193 int phandle, ncells; 194 int off, offset; 195 int ret, length; 196 int i, j; 197 int first_phandle = -1; 198 199 phandle = -ENODATA; 200 ncells = -ENODATA; 201 202 /* fdt points to kernel dtb, getting cru phandle and "#clock-cells" */ 203 for (offset = fdt_next_node(fdt, 0, NULL); 204 offset >= 0; 205 offset = fdt_next_node(fdt, offset, NULL)) { 206 comp = fdt_getprop(fdt, offset, "compatible", NULL); 207 if (!comp) 208 continue; 209 210 /* Actually, this is not a good method to get cru node */ 211 off = strlen(comp) - strlen("-cru"); 212 if (off > 0 && !strncmp(comp + off, "-cru", 4)) { 213 phandle = fdt_get_phandle(fdt, offset); 214 ncells = fdtdec_get_int(fdt, offset, 215 "#clock-cells", -ENODATA); 216 break; 217 } 218 } 219 220 if (phandle == -ENODATA || ncells == -ENODATA) 221 return 0; 222 223 debug("%s: target cru: clock-cells:%d, phandle:0x%x\n", 224 __func__, ncells, fdt32_to_cpu(phandle)); 225 226 /* Try to fixup all cru phandle from U-Boot dtb nodes */ 227 for (id = 0; id < UCLASS_COUNT; id++) { 228 ret = uclass_get(id, &uc); 229 if (ret) 230 continue; 231 232 if (list_empty(&uc->dev_head)) 233 continue; 234 235 list_for_each_entry(dev, &uc->dev_head, uclass_node) { 236 /* Only U-Boot node go further */ 237 if (!dev_read_bool(dev, "u-boot,dm-pre-reloc")) 238 continue; 239 240 for (i = 0; i < ARRAY_SIZE(props); i++) { 241 if (!dev_read_prop(dev, props[i], &length)) 242 continue; 243 244 clocks = malloc(length); 245 if (!clocks) 246 return -ENOMEM; 247 248 /* Read "props[]" which contains cru phandle */ 249 nclocks = length / sizeof(u32); 250 if (dev_read_u32_array(dev, props[i], 251 clocks, nclocks)) { 252 free(clocks); 253 continue; 254 } 255 256 /* Fixup with kernel cru phandle */ 257 for (j = 0; j < nclocks; j += (ncells + 1)) { 258 /* 259 * Check: update pmucru phandle with cru 260 * phandle by mistake. 261 */ 262 if (first_phandle == -1) 263 first_phandle = clocks[j]; 264 265 if (clocks[j] != first_phandle) 266 printf("WARN: %s: first cru phandle=%d, this=%d\n", 267 dev_read_name(dev), 268 first_phandle, clocks[j]); 269 270 clocks[j] = phandle; 271 } 272 273 /* 274 * Override live dt nodes but not fdt nodes, 275 * because all U-Boot nodes has been imported 276 * to live dt nodes, should use "dev_xxx()". 277 */ 278 dev_write_u32_array(dev, props[i], 279 clocks, nclocks); 280 free(clocks); 281 } 282 } 283 } 284 285 return 0; 286 } 287 288 int init_kernel_dtb(void) 289 { 290 int ret = 0; 291 ulong fdt_addr = 0; 292 293 fdt_addr = env_get_ulong("fdt_addr_r", 16, 0); 294 if (!fdt_addr) { 295 printf("No Found FDT Load Address.\n"); 296 return -1; 297 } 298 299 ret = rockchip_read_dtb_file((void *)fdt_addr); 300 if (ret < 0) { 301 printf("%s dtb in resource read fail\n", __func__); 302 return 0; 303 } 304 305 /* 306 * There is a phandle miss match between U-Boot and kernel dtb node, 307 * the typical is cru phandle, we fixup it in U-Boot live dt nodes. 308 */ 309 phandles_fixup((void *)fdt_addr); 310 311 of_live_build((void *)fdt_addr, (struct device_node **)&gd->of_root); 312 313 dm_scan_fdt((void *)fdt_addr, false); 314 315 gd->fdt_blob = (void *)fdt_addr; 316 317 /* Reserve 'reserved-memory' */ 318 ret = boot_fdt_add_sysmem_rsv_regions((void *)gd->fdt_blob); 319 if (ret) 320 return ret; 321 322 return 0; 323 } 324 #endif 325 326 void board_env_fixup(void) 327 { 328 char *addr_r; 329 #ifdef ENV_MEM_LAYOUT_SETTINGS1 330 const char *env_addr0[] = { 331 "scriptaddr", "pxefile_addr_r", 332 "fdt_addr_r", "kernel_addr_r", "ramdisk_addr_r", 333 }; 334 const char *env_addr1[] = { 335 "scriptaddr1", "pxefile_addr1_r", 336 "fdt_addr1_r", "kernel_addr1_r", "ramdisk_addr1_r", 337 }; 338 int i; 339 340 /* 128M is a typical ram size for most platform, so as default here */ 341 if (gd->ram_size <= SZ_128M) { 342 /* Replace orignal xxx_addr_r */ 343 for (i = 0; i < ARRAY_SIZE(env_addr1); i++) { 344 addr_r = env_get(env_addr1[i]); 345 if (addr_r) 346 env_set(env_addr0[i], addr_r); 347 } 348 } 349 #endif 350 /* If bl32 is disabled, maybe kernel can be load to lower address. */ 351 if (!(gd->flags & GD_FLG_BL32_ENABLED)) { 352 addr_r = env_get("kernel_addr_no_bl32_r"); 353 if (addr_r) 354 env_set("kernel_addr_r", addr_r); 355 } 356 } 357 358 static void early_bootrom_download(void) 359 { 360 if (!tstc()) 361 return; 362 363 gd->console_evt = getc(); 364 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 365 /* ctrl+b */ 366 if (is_hotkey(HK_BROM_DNL)) { 367 printf("Enter bootrom download..."); 368 flushc(); 369 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 370 do_reset(NULL, 0, 0, NULL); 371 printf("failed!\n"); 372 } 373 #endif 374 } 375 376 int board_init(void) 377 { 378 int ret; 379 380 board_debug_uart_init(); 381 early_bootrom_download(); 382 383 #ifdef CONFIG_USING_KERNEL_DTB 384 init_kernel_dtb(); 385 #endif 386 /* 387 * pmucru isn't referenced on some platforms, so pmucru driver can't 388 * probe that the "assigned-clocks" is unused. 389 */ 390 clks_probe(); 391 #ifdef CONFIG_DM_REGULATOR 392 ret = regulators_enable_boot_on(false); 393 if (ret) 394 debug("%s: Cannot enable boot on regulator\n", __func__); 395 #endif 396 397 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN 398 io_domain_init(); 399 #endif 400 401 set_armclk_rate(); 402 403 #ifdef CONFIG_DM_DVFS 404 dvfs_init(true); 405 #endif 406 407 return rk_board_init(); 408 } 409 410 int interrupt_debugger_init(void) 411 { 412 int ret = 0; 413 414 #ifdef CONFIG_ROCKCHIP_DEBUGGER 415 ret = rockchip_debugger_init(); 416 #endif 417 return ret; 418 } 419 420 #if defined(CONFIG_ROCKCHIP_RK1808) && !defined(CONFIG_COPROCESSOR_RK1808) 421 #define PINCTRL_EMMC_BUS8_PATH "/pinctrl/emmc/emmc-bus8" 422 #define PINCTRL_EMMC_CMD_PATH "/pinctrl/emmc/emmc-cmd" 423 #define PINCTRL_EMMC_CLK_PATH "/pinctrl/emmc/emmc-clk" 424 #define PINCTRL_PCFG_PU_2MA_PATH "/pinctrl/pcfg-pull-up-2ma" 425 #define MAX_ROCKCHIP_PINS_ENTRIES 12 426 427 static int rockchip_pinctrl_cfg_fdt_fixup(const char *path, u32 new_phandle) 428 { 429 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 430 const u32 *data; 431 int i, count; 432 int node; 433 434 node = fdt_path_offset(gd->fdt_blob, path); 435 if (node < 0) { 436 debug("%s: can't find: %s\n", __func__, path); 437 return node; 438 } 439 440 data = fdt_getprop(gd->fdt_blob, node, "rockchip,pins", &count); 441 if (!data) { 442 debug("%s: can't find prop \"rockchip,pins\"\n", __func__); 443 return -ENODATA; 444 } 445 446 count /= sizeof(u32); 447 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 448 debug("%s: %d is over max count\n", __func__, count); 449 return -EINVAL; 450 } 451 452 for (i = 0; i < count; i++) 453 cells[i] = data[i]; 454 455 for (i = 0; i < (count >> 2); i++) 456 cells[4 * i + 3] = cpu_to_fdt32(new_phandle); 457 458 fdt_setprop((void *)gd->fdt_blob, node, "rockchip,pins", 459 &cells, count * sizeof(u32)); 460 461 return 0; 462 } 463 #endif 464 465 int board_fdt_fixup(void *blob) 466 { 467 int ret = 0; 468 469 /* 470 * Common fixup for DRM 471 */ 472 #ifdef CONFIG_DRM_ROCKCHIP 473 rockchip_display_fixup(blob); 474 #endif 475 476 /* 477 * Platform fixup: 478 * 479 * - RK3288: Recognize RK3288W by HDMI Revision ID is 0x1A; 480 * - RK1808: MMC strength 2mA; 481 */ 482 #ifdef CONFIG_ROCKCHIP_RK3288 483 if (soc_is_rk3288w()) { 484 ret = fdt_setprop_string(blob, 0, 485 "compatible", "rockchip,rk3288w"); 486 if (ret) 487 printf("fdt set compatible failed: %d\n", ret); 488 } 489 #elif defined(CONFIG_ROCKCHIP_RK1808) && !defined(CONFIG_COPROCESSOR_RK1808) 490 struct tag *t; 491 u32 ph_pu_2ma; 492 493 t = atags_get_tag(ATAG_SOC_INFO); 494 if (!t) 495 return 0; 496 497 debug("soc=0x%x, flags=0x%x\n", t->u.soc.name, t->u.soc.flags); 498 499 if (t->u.soc.flags != SOC_FLAGS_ET00) 500 return 0; 501 502 ph_pu_2ma = fdt_get_phandle(gd->fdt_blob, 503 fdt_path_offset(gd->fdt_blob, PINCTRL_PCFG_PU_2MA_PATH)); 504 if (!ph_pu_2ma) { 505 debug("Can't find: %s\n", PINCTRL_PCFG_PU_2MA_PATH); 506 return -EINVAL; 507 } 508 509 ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_BUS8_PATH, ph_pu_2ma); 510 ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_CMD_PATH, ph_pu_2ma); 511 ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_CLK_PATH, ph_pu_2ma); 512 #endif 513 514 return ret; 515 } 516 517 #ifdef CONFIG_ARM64_BOOT_AARCH32 518 /* 519 * Fixup MMU region attr for OP-TEE on ARMv8 CPU: 520 * 521 * What ever U-Boot is 64-bit or 32-bit mode, the OP-TEE is always 64-bit mode. 522 * 523 * Command for OP-TEE: 524 * 64-bit mode: dcache is always enabled; 525 * 32-bit mode: dcache is always disabled(Due to some unknown issue); 526 * 527 * Command for U-Boot: 528 * 64-bit mode: MMU table is static defined in rkxxx.c file, all memory 529 * regions are mapped. That's good to match OP-TEE MMU policy. 530 * 531 * 32-bit mode: MMU table is setup according to gd->bd->bi_dram[..] where 532 * the OP-TEE region has been reserved, so it can not be 533 * mapped(i.e. dcache is disabled). That's also good to match 534 * OP-TEE MMU policy. 535 * 536 * For the data coherence when communication between U-Boot and OP-TEE, U-Boot 537 * should follow OP-TEE MMU policy. 538 * 539 * Here is the special: 540 * When CONFIG_ARM64_BOOT_AARCH32 is enabled, U-Boot is 32-bit mode while 541 * OP-TEE is still 64-bit mode. U-Boot would not map MMU table for OP-TEE 542 * region(but OP-TEE requires it cacheable) so we fixup here. 543 */ 544 int board_initr_caches_fixup(void) 545 { 546 struct memblock mem; 547 548 mem = param_parse_optee_mem(); 549 if (mem.size) 550 mmu_set_region_dcache_behaviour(mem.base, mem.size, 551 DCACHE_WRITEBACK); 552 return 0; 553 } 554 #endif 555 556 void board_quiesce_devices(void) 557 { 558 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 559 /* Destroy atags makes next warm boot safer */ 560 atags_destroy(); 561 #endif 562 563 #if defined(CONFIG_CONSOLE_RECORD) 564 /* Print record console data */ 565 console_record_print_purge(); 566 #endif 567 } 568 569 void enable_caches(void) 570 { 571 icache_enable(); 572 dcache_enable(); 573 } 574 575 #ifdef CONFIG_LMB 576 /* 577 * Using last bi_dram[...] to initialize "bootm_low" and "bootm_mapsize". 578 * This makes lmb_alloc_base() always alloc from tail of sdram. 579 * If we don't assign it, bi_dram[0] is used by default and it may cause 580 * lmb_alloc_base() fail when bi_dram[0] range is small. 581 */ 582 void board_lmb_reserve(struct lmb *lmb) 583 { 584 u64 start, size; 585 char bootm_low[32]; 586 char bootm_mapsize[32]; 587 int i; 588 589 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 590 if (!gd->bd->bi_dram[i].size) 591 break; 592 } 593 594 start = gd->bd->bi_dram[i - 1].start; 595 size = gd->bd->bi_dram[i - 1].size; 596 597 /* 598 * 32-bit kernel: ramdisk/fdt shouldn't be loaded to highmem area(768MB+), 599 * otherwise "Unable to handle kernel paging request at virtual address ...". 600 * 601 * So that we hope limit highest address at 768M, but there comes the the 602 * problem: ramdisk is a compressed image and it expands after descompress, 603 * so it accesses 768MB+ and brings the above "Unable to handle kernel ...". 604 * 605 * We make a appointment that the highest memory address is 512MB, it 606 * makes lmb alloc safer. 607 */ 608 #ifndef CONFIG_ARM64 609 if (start >= ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) { 610 start = gd->bd->bi_dram[i - 2].start; 611 size = gd->bd->bi_dram[i - 2].size; 612 } 613 614 if ((start + size) > ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) 615 size = (u64)CONFIG_SYS_SDRAM_BASE + SZ_512M - start; 616 #endif 617 sprintf(bootm_low, "0x%llx", start); 618 sprintf(bootm_mapsize, "0x%llx", size); 619 env_set("bootm_low", bootm_low); 620 env_set("bootm_mapsize", bootm_mapsize); 621 } 622 #endif 623 624 #ifdef CONFIG_BIDRAM 625 int board_bidram_reserve(struct bidram *bidram) 626 { 627 struct memblock mem; 628 int ret; 629 630 /* ATF */ 631 mem = param_parse_atf_mem(); 632 ret = bidram_reserve(MEMBLK_ID_ATF, mem.base, mem.size); 633 if (ret) 634 return ret; 635 636 /* PSTORE/ATAGS/SHM */ 637 mem = param_parse_common_resv_mem(); 638 ret = bidram_reserve(MEMBLK_ID_SHM, mem.base, mem.size); 639 if (ret) 640 return ret; 641 642 /* OP-TEE */ 643 mem = param_parse_optee_mem(); 644 ret = bidram_reserve(MEMBLK_ID_OPTEE, mem.base, mem.size); 645 if (ret) 646 return ret; 647 648 return 0; 649 } 650 651 parse_fn_t board_bidram_parse_fn(void) 652 { 653 return param_parse_ddr_mem; 654 } 655 #endif 656 657 #ifdef CONFIG_ROCKCHIP_AMP 658 void cpu_secondary_init_r(void) 659 { 660 amp_cpus_on(); 661 } 662 #endif 663 664 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \ 665 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS) 666 int board_init_f_init_serial(void) 667 { 668 struct tag *t = atags_get_tag(ATAG_SERIAL); 669 670 if (t) { 671 gd->serial.using_pre_serial = t->u.serial.enable; 672 gd->serial.addr = t->u.serial.addr; 673 gd->serial.baudrate = t->u.serial.baudrate; 674 gd->serial.id = t->u.serial.id; 675 676 debug("%s: enable=%d, addr=0x%lx, baudrate=%d, id=%d\n", 677 __func__, gd->serial.using_pre_serial, 678 gd->serial.addr, gd->serial.baudrate, 679 gd->serial.id); 680 } 681 682 return 0; 683 } 684 #endif 685 686 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) 687 #include <fdt_support.h> 688 #include <usb.h> 689 #include <usb/dwc2_udc.h> 690 691 static struct dwc2_plat_otg_data otg_data = { 692 .rx_fifo_sz = 512, 693 .np_tx_fifo_sz = 16, 694 .tx_fifo_sz = 128, 695 }; 696 697 int board_usb_init(int index, enum usb_init_type init) 698 { 699 int node; 700 fdt_addr_t addr; 701 const fdt32_t *reg; 702 const void *blob = gd->fdt_blob; 703 704 /* find the usb_otg node */ 705 node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); 706 707 retry: 708 if (node > 0) { 709 reg = fdt_getprop(blob, node, "reg", NULL); 710 if (!reg) 711 return -EINVAL; 712 713 addr = fdt_translate_address(blob, node, reg); 714 if (addr == OF_BAD_ADDR) { 715 pr_err("Not found usb_otg address\n"); 716 return -EINVAL; 717 } 718 719 #if defined(CONFIG_ROCKCHIP_RK3288) 720 if (addr != 0xff580000) { 721 node = fdt_node_offset_by_compatible(blob, node, 722 "snps,dwc2"); 723 goto retry; 724 } 725 #endif 726 } else { 727 /* 728 * With kernel dtb support, rk3288 dwc2 otg node 729 * use the rockchip legacy dwc2 driver "dwc_otg_310" 730 * with the compatible "rockchip,rk3288_usb20_otg", 731 * and rk3368 also use the "dwc_otg_310" driver with 732 * the compatible "rockchip,rk3368-usb". 733 */ 734 #if defined(CONFIG_ROCKCHIP_RK3288) 735 node = fdt_node_offset_by_compatible(blob, -1, 736 "rockchip,rk3288_usb20_otg"); 737 #elif defined(CONFIG_ROCKCHIP_RK3368) 738 node = fdt_node_offset_by_compatible(blob, -1, 739 "rockchip,rk3368-usb"); 740 #endif 741 if (node > 0) { 742 goto retry; 743 } else { 744 pr_err("Not found usb_otg device\n"); 745 return -ENODEV; 746 } 747 } 748 749 otg_data.regs_otg = (uintptr_t)addr; 750 751 return dwc2_udc_probe(&otg_data); 752 } 753 754 int board_usb_cleanup(int index, enum usb_init_type init) 755 { 756 return 0; 757 } 758 #endif 759