1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <amp.h> 9 #include <bidram.h> 10 #include <boot_rkimg.h> 11 #include <cli.h> 12 #include <clk.h> 13 #include <console.h> 14 #include <debug_uart.h> 15 #include <dm.h> 16 #include <dvfs.h> 17 #include <io-domain.h> 18 #include <key.h> 19 #include <memblk.h> 20 #include <misc.h> 21 #include <of_live.h> 22 #include <ram.h> 23 #include <rockchip_debugger.h> 24 #include <syscon.h> 25 #include <sysmem.h> 26 #include <video_rockchip.h> 27 #include <asm/io.h> 28 #include <asm/gpio.h> 29 #include <dm/uclass-internal.h> 30 #include <dm/root.h> 31 #include <power/charge_display.h> 32 #include <power/regulator.h> 33 #include <asm/arch/boot_mode.h> 34 #include <asm/arch/clock.h> 35 #include <asm/arch/cpu.h> 36 #include <asm/arch/hotkey.h> 37 #include <asm/arch/param.h> 38 #include <asm/arch/periph.h> 39 #include <asm/arch/resource_img.h> 40 #include <asm/arch/rk_atags.h> 41 #include <asm/arch/vendor.h> 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 __weak int rk_board_late_init(void) 46 { 47 return 0; 48 } 49 50 __weak int rk_board_fdt_fixup(void *blob) 51 { 52 return 0; 53 } 54 55 __weak int soc_clk_dump(void) 56 { 57 return 0; 58 } 59 60 __weak int set_armclk_rate(void) 61 { 62 return 0; 63 } 64 65 __weak int rk_board_init(void) 66 { 67 return 0; 68 } 69 70 /* 71 * define serialno max length, the max length is 512 Bytes 72 * The remaining bytes are used to ensure that the first 512 bytes 73 * are valid when executing 'env_set("serial#", value)'. 74 */ 75 #define VENDOR_SN_MAX 513 76 #define CPUID_LEN 0x10 77 #define CPUID_OFF 0x07 78 79 static int rockchip_set_ethaddr(void) 80 { 81 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 82 char buf[ARP_HLEN_ASCII + 1]; 83 u8 ethaddr[ARP_HLEN]; 84 int ret; 85 86 ret = vendor_storage_read(VENDOR_LAN_MAC_ID, ethaddr, sizeof(ethaddr)); 87 if (ret > 0 && is_valid_ethaddr(ethaddr)) { 88 sprintf(buf, "%pM", ethaddr); 89 env_set("ethaddr", buf); 90 } 91 #endif 92 return 0; 93 } 94 95 static int rockchip_set_serialno(void) 96 { 97 u8 low[CPUID_LEN / 2], high[CPUID_LEN / 2]; 98 u8 cpuid[CPUID_LEN] = {0}; 99 char serialno_str[VENDOR_SN_MAX]; 100 int ret = 0, i; 101 u64 serialno; 102 103 /* Read serial number from vendor storage part */ 104 memset(serialno_str, 0, VENDOR_SN_MAX); 105 106 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 107 ret = vendor_storage_read(VENDOR_SN_ID, serialno_str, (VENDOR_SN_MAX-1)); 108 if (ret > 0) { 109 env_set("serial#", serialno_str); 110 } else { 111 #endif 112 #ifdef CONFIG_ROCKCHIP_EFUSE 113 struct udevice *dev; 114 115 /* retrieve the device */ 116 ret = uclass_get_device_by_driver(UCLASS_MISC, 117 DM_GET_DRIVER(rockchip_efuse), 118 &dev); 119 if (ret) { 120 printf("%s: could not find efuse device\n", __func__); 121 return ret; 122 } 123 124 /* read the cpu_id range from the efuses */ 125 ret = misc_read(dev, CPUID_OFF, &cpuid, sizeof(cpuid)); 126 if (ret) { 127 printf("%s: read cpuid from efuses failed, ret=%d\n", 128 __func__, ret); 129 return ret; 130 } 131 #else 132 /* generate random cpuid */ 133 for (i = 0; i < CPUID_LEN; i++) 134 cpuid[i] = (u8)(rand()); 135 #endif 136 /* Generate the serial number based on CPU ID */ 137 for (i = 0; i < 8; i++) { 138 low[i] = cpuid[1 + (i << 1)]; 139 high[i] = cpuid[i << 1]; 140 } 141 142 serialno = crc32_no_comp(0, low, 8); 143 serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; 144 snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno); 145 146 env_set("serial#", serialno_str); 147 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 148 } 149 #endif 150 151 return ret; 152 } 153 154 #if defined(CONFIG_USB_FUNCTION_FASTBOOT) 155 int fb_set_reboot_flag(void) 156 { 157 printf("Setting reboot to fastboot flag ...\n"); 158 writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG); 159 160 return 0; 161 } 162 #endif 163 164 #ifdef CONFIG_ROCKCHIP_USB_BOOT 165 static int boot_from_udisk(void) 166 { 167 struct blk_desc *desc; 168 char *devtype; 169 char *devnum; 170 171 devtype = env_get("devtype"); 172 devnum = env_get("devnum"); 173 174 /* Booting priority: mmc1 > udisk */ 175 if (!strcmp(devtype, "mmc") && !strcmp(devnum, "1")) 176 return 0; 177 178 if (!run_command("usb start", -1)) { 179 desc = blk_get_devnum_by_type(IF_TYPE_USB, 0); 180 if (!desc) { 181 printf("No usb device found\n"); 182 return -ENODEV; 183 } 184 185 if (!run_command("rkimgtest usb 0", -1)) { 186 rockchip_set_bootdev(desc); 187 env_set("devtype", "usb"); 188 env_set("devnum", "0"); 189 printf("Boot from usb 0\n"); 190 } else { 191 printf("No usb dev 0 found\n"); 192 return -ENODEV; 193 } 194 } 195 196 return 0; 197 } 198 #endif 199 200 static void cmdline_handle(void) 201 { 202 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 203 struct tag *t; 204 205 t = atags_get_tag(ATAG_PUB_KEY); 206 if (t) { 207 /* Pass if efuse/otp programmed */ 208 if (t->u.pub_key.flag == PUBKEY_FUSE_PROGRAMMED) 209 env_update("bootargs", "fuse.programmed=1"); 210 else 211 env_update("bootargs", "fuse.programmed=0"); 212 } 213 #endif 214 } 215 216 int board_late_init(void) 217 { 218 rockchip_set_ethaddr(); 219 rockchip_set_serialno(); 220 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 221 setup_boot_mode(); 222 #endif 223 #ifdef CONFIG_ROCKCHIP_USB_BOOT 224 boot_from_udisk(); 225 #endif 226 #ifdef CONFIG_DM_CHARGE_DISPLAY 227 charge_display(); 228 #endif 229 #ifdef CONFIG_DRM_ROCKCHIP 230 rockchip_show_logo(); 231 #endif 232 soc_clk_dump(); 233 cmdline_handle(); 234 235 return rk_board_late_init(); 236 } 237 238 #ifdef CONFIG_USING_KERNEL_DTB 239 /* Here, only fixup cru phandle, pmucru is not included */ 240 static int phandles_fixup(void *fdt) 241 { 242 const char *props[] = { "clocks", "assigned-clocks" }; 243 struct udevice *dev; 244 struct uclass *uc; 245 const char *comp; 246 u32 id, nclocks; 247 u32 *clocks; 248 int phandle, ncells; 249 int off, offset; 250 int ret, length; 251 int i, j; 252 int first_phandle = -1; 253 254 phandle = -ENODATA; 255 ncells = -ENODATA; 256 257 /* fdt points to kernel dtb, getting cru phandle and "#clock-cells" */ 258 for (offset = fdt_next_node(fdt, 0, NULL); 259 offset >= 0; 260 offset = fdt_next_node(fdt, offset, NULL)) { 261 comp = fdt_getprop(fdt, offset, "compatible", NULL); 262 if (!comp) 263 continue; 264 265 /* Actually, this is not a good method to get cru node */ 266 off = strlen(comp) - strlen("-cru"); 267 if (off > 0 && !strncmp(comp + off, "-cru", 4)) { 268 phandle = fdt_get_phandle(fdt, offset); 269 ncells = fdtdec_get_int(fdt, offset, 270 "#clock-cells", -ENODATA); 271 break; 272 } 273 } 274 275 if (phandle == -ENODATA || ncells == -ENODATA) 276 return 0; 277 278 debug("%s: target cru: clock-cells:%d, phandle:0x%x\n", 279 __func__, ncells, fdt32_to_cpu(phandle)); 280 281 /* Try to fixup all cru phandle from U-Boot dtb nodes */ 282 for (id = 0; id < UCLASS_COUNT; id++) { 283 ret = uclass_get(id, &uc); 284 if (ret) 285 continue; 286 287 if (list_empty(&uc->dev_head)) 288 continue; 289 290 list_for_each_entry(dev, &uc->dev_head, uclass_node) { 291 /* Only U-Boot node go further */ 292 if (!dev_read_bool(dev, "u-boot,dm-pre-reloc") && 293 !dev_read_bool(dev, "u-boot,dm-spl")) 294 continue; 295 296 for (i = 0; i < ARRAY_SIZE(props); i++) { 297 if (!dev_read_prop(dev, props[i], &length)) 298 continue; 299 300 clocks = malloc(length); 301 if (!clocks) 302 return -ENOMEM; 303 304 /* Read "props[]" which contains cru phandle */ 305 nclocks = length / sizeof(u32); 306 if (dev_read_u32_array(dev, props[i], 307 clocks, nclocks)) { 308 free(clocks); 309 continue; 310 } 311 312 /* Fixup with kernel cru phandle */ 313 for (j = 0; j < nclocks; j += (ncells + 1)) { 314 /* 315 * Check: update pmucru phandle with cru 316 * phandle by mistake. 317 */ 318 if (first_phandle == -1) 319 first_phandle = clocks[j]; 320 321 if (clocks[j] != first_phandle) { 322 debug("WARN: %s: first cru phandle=%d, this=%d\n", 323 dev_read_name(dev), 324 first_phandle, clocks[j]); 325 continue; 326 } 327 328 clocks[j] = phandle; 329 } 330 331 /* 332 * Override live dt nodes but not fdt nodes, 333 * because all U-Boot nodes has been imported 334 * to live dt nodes, should use "dev_xxx()". 335 */ 336 dev_write_u32_array(dev, props[i], 337 clocks, nclocks); 338 free(clocks); 339 } 340 } 341 } 342 343 return 0; 344 } 345 346 int init_kernel_dtb(void) 347 { 348 ulong fdt_addr; 349 int ret; 350 351 fdt_addr = env_get_ulong("fdt_addr_r", 16, 0); 352 if (!fdt_addr) { 353 printf("No Found FDT Load Address.\n"); 354 return -1; 355 } 356 357 ret = rockchip_read_dtb_file((void *)fdt_addr); 358 if (ret < 0) { 359 if (!fdt_check_header(gd->fdt_blob_kern)) { 360 fdt_addr = (ulong)memalign(ARCH_DMA_MINALIGN, 361 fdt_totalsize(gd->fdt_blob_kern)); 362 if (!fdt_addr) 363 return -ENOMEM; 364 365 memcpy((void *)fdt_addr, gd->fdt_blob_kern, 366 fdt_totalsize(gd->fdt_blob_kern)); 367 printf("DTB: embedded kern.dtb\n"); 368 } else { 369 printf("Failed to get kernel dtb, ret=%d\n", ret); 370 return ret; 371 } 372 } 373 374 gd->fdt_blob = (void *)fdt_addr; 375 376 /* 377 * There is a phandle miss match between U-Boot and kernel dtb node, 378 * the typical is cru phandle, we fixup it in U-Boot live dt nodes. 379 */ 380 phandles_fixup((void *)gd->fdt_blob); 381 382 of_live_build((void *)gd->fdt_blob, (struct device_node **)&gd->of_root); 383 dm_scan_fdt((void *)gd->fdt_blob, false); 384 385 /* Reserve 'reserved-memory' */ 386 ret = boot_fdt_add_sysmem_rsv_regions((void *)gd->fdt_blob); 387 if (ret) 388 return ret; 389 390 return 0; 391 } 392 #endif 393 394 void board_env_fixup(void) 395 { 396 struct memblock mem; 397 ulong u_addr_r; 398 phys_size_t end; 399 char *addr_r; 400 401 #ifdef ENV_MEM_LAYOUT_SETTINGS1 402 const char *env_addr0[] = { 403 "scriptaddr", "pxefile_addr_r", 404 "fdt_addr_r", "kernel_addr_r", "ramdisk_addr_r", 405 }; 406 const char *env_addr1[] = { 407 "scriptaddr1", "pxefile_addr1_r", 408 "fdt_addr1_r", "kernel_addr1_r", "ramdisk_addr1_r", 409 }; 410 int i; 411 412 /* 128M is a typical ram size for most platform, so as default here */ 413 if (gd->ram_size <= SZ_128M) { 414 /* Replace orignal xxx_addr_r */ 415 for (i = 0; i < ARRAY_SIZE(env_addr1); i++) { 416 addr_r = env_get(env_addr1[i]); 417 if (addr_r) 418 env_set(env_addr0[i], addr_r); 419 } 420 } 421 #endif 422 /* If bl32 is disabled, maybe kernel can be load to lower address. */ 423 if (!(gd->flags & GD_FLG_BL32_ENABLED)) { 424 addr_r = env_get("kernel_addr_no_bl32_r"); 425 if (addr_r) 426 env_set("kernel_addr_r", addr_r); 427 /* If bl32 is enlarged, we move ramdisk addr right behind it */ 428 } else { 429 mem = param_parse_optee_mem(); 430 end = mem.base + mem.size; 431 u_addr_r = env_get_ulong("ramdisk_addr_r", 16, 0); 432 if (u_addr_r >= mem.base && u_addr_r < end) 433 env_set_hex("ramdisk_addr_r", end); 434 } 435 } 436 437 static void early_download_init(void) 438 { 439 #if defined(CONFIG_PWRKEY_DNL_TRIGGER_NUM) && \ 440 (CONFIG_PWRKEY_DNL_TRIGGER_NUM > 0) 441 if (pwrkey_download_init()) 442 printf("Pwrkey download init failed\n"); 443 #endif 444 445 if (!tstc()) 446 return; 447 448 gd->console_evt = getc(); 449 if (gd->console_evt <= 0x1a) /* 'z' */ 450 printf("Hotkey: ctrl+%c\n", (gd->console_evt + 'a' - 1)); 451 452 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 453 if (is_hotkey(HK_BROM_DNL)) { 454 printf("Enter bootrom download..."); 455 flushc(); 456 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 457 do_reset(NULL, 0, 0, NULL); 458 printf("failed!\n"); 459 } 460 #endif 461 } 462 463 int board_init(void) 464 { 465 board_debug_uart_init(); 466 467 #ifdef DEBUG 468 soc_clk_dump(); 469 #endif 470 471 #ifdef CONFIG_USING_KERNEL_DTB 472 init_kernel_dtb(); 473 #endif 474 early_download_init(); 475 476 /* 477 * pmucru isn't referenced on some platforms, so pmucru driver can't 478 * probe that the "assigned-clocks" is unused. 479 */ 480 clks_probe(); 481 #ifdef CONFIG_DM_REGULATOR 482 if (regulators_enable_boot_on(is_hotkey(HK_REGULATOR))) 483 debug("%s: Can't enable boot on regulator\n", __func__); 484 #endif 485 486 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN 487 io_domain_init(); 488 #endif 489 490 set_armclk_rate(); 491 492 #ifdef CONFIG_DM_DVFS 493 dvfs_init(true); 494 #endif 495 496 return rk_board_init(); 497 } 498 499 int interrupt_debugger_init(void) 500 { 501 #ifdef CONFIG_ROCKCHIP_DEBUGGER 502 return rockchip_debugger_init(); 503 #else 504 return 0; 505 #endif 506 } 507 508 int board_fdt_fixup(void *blob) 509 { 510 /* Common fixup for DRM */ 511 #ifdef CONFIG_DRM_ROCKCHIP 512 rockchip_display_fixup(blob); 513 #endif 514 515 return rk_board_fdt_fixup(blob); 516 } 517 518 #ifdef CONFIG_ARM64_BOOT_AARCH32 519 /* 520 * Fixup MMU region attr for OP-TEE on ARMv8 CPU: 521 * 522 * What ever U-Boot is 64-bit or 32-bit mode, the OP-TEE is always 64-bit mode. 523 * 524 * Command for OP-TEE: 525 * 64-bit mode: dcache is always enabled; 526 * 32-bit mode: dcache is always disabled(Due to some unknown issue); 527 * 528 * Command for U-Boot: 529 * 64-bit mode: MMU table is static defined in rkxxx.c file, all memory 530 * regions are mapped. That's good to match OP-TEE MMU policy. 531 * 532 * 32-bit mode: MMU table is setup according to gd->bd->bi_dram[..] where 533 * the OP-TEE region has been reserved, so it can not be 534 * mapped(i.e. dcache is disabled). That's also good to match 535 * OP-TEE MMU policy. 536 * 537 * For the data coherence when communication between U-Boot and OP-TEE, U-Boot 538 * should follow OP-TEE MMU policy. 539 * 540 * Here is the special: 541 * When CONFIG_ARM64_BOOT_AARCH32 is enabled, U-Boot is 32-bit mode while 542 * OP-TEE is still 64-bit mode. U-Boot would not map MMU table for OP-TEE 543 * region(but OP-TEE requires it cacheable) so we fixup here. 544 */ 545 int board_initr_caches_fixup(void) 546 { 547 struct memblock mem; 548 549 mem = param_parse_optee_mem(); 550 if (mem.size) 551 mmu_set_region_dcache_behaviour(mem.base, mem.size, 552 DCACHE_WRITEBACK); 553 return 0; 554 } 555 #endif 556 557 void arch_preboot_os(uint32_t bootm_state) 558 { 559 if (bootm_state & BOOTM_STATE_OS_PREP) 560 hotkey_run(HK_CLI_OS_PRE); 561 } 562 563 void board_quiesce_devices(void) 564 { 565 hotkey_run(HK_CMDLINE); 566 hotkey_run(HK_CLI_OS_GO); 567 568 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 569 /* Destroy atags makes next warm boot safer */ 570 atags_destroy(); 571 #endif 572 573 #if defined(CONFIG_CONSOLE_RECORD) 574 /* Print record console data */ 575 console_record_print_purge(); 576 #endif 577 } 578 579 void enable_caches(void) 580 { 581 icache_enable(); 582 dcache_enable(); 583 } 584 585 #ifdef CONFIG_LMB 586 /* 587 * Using last bi_dram[...] to initialize "bootm_low" and "bootm_mapsize". 588 * This makes lmb_alloc_base() always alloc from tail of sdram. 589 * If we don't assign it, bi_dram[0] is used by default and it may cause 590 * lmb_alloc_base() fail when bi_dram[0] range is small. 591 */ 592 void board_lmb_reserve(struct lmb *lmb) 593 { 594 char bootm_mapsize[32]; 595 char bootm_low[32]; 596 u64 start, size; 597 int i; 598 599 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 600 if (!gd->bd->bi_dram[i].size) 601 break; 602 } 603 604 start = gd->bd->bi_dram[i - 1].start; 605 size = gd->bd->bi_dram[i - 1].size; 606 607 /* 608 * 32-bit kernel: ramdisk/fdt shouldn't be loaded to highmem area(768MB+), 609 * otherwise "Unable to handle kernel paging request at virtual address ...". 610 * 611 * So that we hope limit highest address at 768M, but there comes the the 612 * problem: ramdisk is a compressed image and it expands after descompress, 613 * so it accesses 768MB+ and brings the above "Unable to handle kernel ...". 614 * 615 * We make a appointment that the highest memory address is 512MB, it 616 * makes lmb alloc safer. 617 */ 618 #ifndef CONFIG_ARM64 619 if (start >= ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) { 620 start = gd->bd->bi_dram[i - 2].start; 621 size = gd->bd->bi_dram[i - 2].size; 622 } 623 624 if ((start + size) > ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) 625 size = (u64)CONFIG_SYS_SDRAM_BASE + SZ_512M - start; 626 #endif 627 sprintf(bootm_low, "0x%llx", start); 628 sprintf(bootm_mapsize, "0x%llx", size); 629 env_set("bootm_low", bootm_low); 630 env_set("bootm_mapsize", bootm_mapsize); 631 } 632 #endif 633 634 #ifdef CONFIG_BIDRAM 635 int board_bidram_reserve(struct bidram *bidram) 636 { 637 struct memblock mem; 638 int ret; 639 640 /* ATF */ 641 mem = param_parse_atf_mem(); 642 ret = bidram_reserve(MEMBLK_ID_ATF, mem.base, mem.size); 643 if (ret) 644 return ret; 645 646 /* PSTORE/ATAGS/SHM */ 647 mem = param_parse_common_resv_mem(); 648 ret = bidram_reserve(MEMBLK_ID_SHM, mem.base, mem.size); 649 if (ret) 650 return ret; 651 652 /* OP-TEE */ 653 mem = param_parse_optee_mem(); 654 ret = bidram_reserve(MEMBLK_ID_OPTEE, mem.base, mem.size); 655 if (ret) 656 return ret; 657 658 return 0; 659 } 660 661 parse_fn_t board_bidram_parse_fn(void) 662 { 663 return param_parse_ddr_mem; 664 } 665 #endif 666 667 #ifdef CONFIG_ROCKCHIP_AMP 668 void cpu_secondary_init_r(void) 669 { 670 amp_cpus_on(); 671 } 672 #endif 673 674 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \ 675 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS) 676 int board_init_f_init_serial(void) 677 { 678 struct tag *t = atags_get_tag(ATAG_SERIAL); 679 680 if (t) { 681 gd->serial.using_pre_serial = t->u.serial.enable; 682 gd->serial.addr = t->u.serial.addr; 683 gd->serial.baudrate = t->u.serial.baudrate; 684 gd->serial.id = t->u.serial.id; 685 686 debug("%s: enable=%d, addr=0x%lx, baudrate=%d, id=%d\n", 687 __func__, gd->serial.using_pre_serial, 688 gd->serial.addr, gd->serial.baudrate, 689 gd->serial.id); 690 } 691 692 return 0; 693 } 694 #endif 695 696 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) 697 #include <fdt_support.h> 698 #include <usb.h> 699 #include <usb/dwc2_udc.h> 700 701 static struct dwc2_plat_otg_data otg_data = { 702 .rx_fifo_sz = 512, 703 .np_tx_fifo_sz = 16, 704 .tx_fifo_sz = 128, 705 }; 706 707 int board_usb_init(int index, enum usb_init_type init) 708 { 709 const void *blob = gd->fdt_blob; 710 const fdt32_t *reg; 711 fdt_addr_t addr; 712 int node; 713 714 /* find the usb_otg node */ 715 node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); 716 717 retry: 718 if (node > 0) { 719 reg = fdt_getprop(blob, node, "reg", NULL); 720 if (!reg) 721 return -EINVAL; 722 723 addr = fdt_translate_address(blob, node, reg); 724 if (addr == OF_BAD_ADDR) { 725 pr_err("Not found usb_otg address\n"); 726 return -EINVAL; 727 } 728 729 #if defined(CONFIG_ROCKCHIP_RK3288) 730 if (addr != 0xff580000) { 731 node = fdt_node_offset_by_compatible(blob, node, 732 "snps,dwc2"); 733 goto retry; 734 } 735 #endif 736 } else { 737 /* 738 * With kernel dtb support, rk3288 dwc2 otg node 739 * use the rockchip legacy dwc2 driver "dwc_otg_310" 740 * with the compatible "rockchip,rk3288_usb20_otg", 741 * and rk3368 also use the "dwc_otg_310" driver with 742 * the compatible "rockchip,rk3368-usb". 743 */ 744 #if defined(CONFIG_ROCKCHIP_RK3288) 745 node = fdt_node_offset_by_compatible(blob, -1, 746 "rockchip,rk3288_usb20_otg"); 747 #elif defined(CONFIG_ROCKCHIP_RK3368) 748 node = fdt_node_offset_by_compatible(blob, -1, 749 "rockchip,rk3368-usb"); 750 #endif 751 if (node > 0) { 752 goto retry; 753 } else { 754 pr_err("Not found usb_otg device\n"); 755 return -ENODEV; 756 } 757 } 758 759 otg_data.regs_otg = (uintptr_t)addr; 760 761 return dwc2_udc_probe(&otg_data); 762 } 763 764 int board_usb_cleanup(int index, enum usb_init_type init) 765 { 766 return 0; 767 } 768 #endif 769