xref: /rk3399_rockchip-uboot/arch/arm/mach-rockchip/board.c (revision 0986a7dda1c55af4d329d51f1b4e7c0964db5abc) 
1 /*
2  * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 #include <common.h>
7 #include <amp.h>
8 #include <clk.h>
9 #include <bidram.h>
10 #include <dm.h>
11 #include <debug_uart.h>
12 #include <memblk.h>
13 #include <ram.h>
14 #include <syscon.h>
15 #include <sysmem.h>
16 #include <asm/io.h>
17 #include <asm/arch/vendor.h>
18 #include <misc.h>
19 #include <asm/gpio.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/periph.h>
22 #include <asm/arch/boot_mode.h>
23 #include <asm/arch/hotkey.h>
24 #include <asm/arch/rk_atags.h>
25 #include <asm/arch/param.h>
26 #ifdef CONFIG_DM_CHARGE_DISPLAY
27 #include <power/charge_display.h>
28 #endif
29 #ifdef CONFIG_DM_DVFS
30 #include <dvfs.h>
31 #endif
32 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN
33 #include <io-domain.h>
34 #endif
35 #ifdef CONFIG_DM_REGULATOR
36 #include <power/regulator.h>
37 #endif
38 #ifdef CONFIG_DRM_ROCKCHIP
39 #include <video_rockchip.h>
40 #endif
41 #ifdef CONFIG_ROCKCHIP_DEBUGGER
42 #include <rockchip_debugger.h>
43 #endif
44 #include <of_live.h>
45 #include <dm/root.h>
46 #include <console.h>
47 
48 DECLARE_GLOBAL_DATA_PTR;
49 /* define serialno max length, the max length is 512 Bytes
50  * The remaining bytes are used to ensure that the first 512 bytes
51  * are valid when executing 'env_set("serial#", value)'.
52  */
53 #define VENDOR_SN_MAX	513
54 #define CPUID_LEN       0x10
55 #define CPUID_OFF       0x7
56 
57 static int rockchip_set_ethaddr(void)
58 {
59 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
60 	int ret;
61 	u8 ethaddr[ARP_HLEN];
62 	char buf[ARP_HLEN_ASCII + 1];
63 
64 	ret = vendor_storage_read(VENDOR_LAN_MAC_ID, ethaddr, sizeof(ethaddr));
65 	if (ret > 0 && is_valid_ethaddr(ethaddr)) {
66 		sprintf(buf, "%pM", ethaddr);
67 		env_set("ethaddr", buf);
68 	}
69 #endif
70 	return 0;
71 }
72 
73 static int rockchip_set_serialno(void)
74 {
75 	char serialno_str[VENDOR_SN_MAX];
76 	int ret = 0, i;
77 	u8 cpuid[CPUID_LEN] = {0};
78 	u8 low[CPUID_LEN / 2], high[CPUID_LEN / 2];
79 	u64 serialno;
80 
81 	/* Read serial number from vendor storage part */
82 	memset(serialno_str, 0, VENDOR_SN_MAX);
83 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
84 	ret = vendor_storage_read(VENDOR_SN_ID, serialno_str, (VENDOR_SN_MAX-1));
85 	if (ret > 0) {
86 		env_set("serial#", serialno_str);
87 	} else {
88 #endif
89 #ifdef CONFIG_ROCKCHIP_EFUSE
90 		struct udevice *dev;
91 
92 		/* retrieve the device */
93 		ret = uclass_get_device_by_driver(UCLASS_MISC,
94 						  DM_GET_DRIVER(rockchip_efuse), &dev);
95 		if (ret) {
96 			printf("%s: could not find efuse device\n", __func__);
97 			return ret;
98 		}
99 		/* read the cpu_id range from the efuses */
100 		ret = misc_read(dev, CPUID_OFF, &cpuid, sizeof(cpuid));
101 		if (ret) {
102 			printf("%s: reading cpuid from the efuses failed\n", __func__);
103 			return ret;
104 		}
105 #else
106 		/* generate random cpuid */
107 		for (i = 0; i < CPUID_LEN; i++) {
108 			cpuid[i] = (u8)(rand());
109 		}
110 #endif
111 		/* Generate the serial number based on CPU ID */
112 		for (i = 0; i < 8; i++) {
113 			low[i] = cpuid[1 + (i << 1)];
114 			high[i] = cpuid[i << 1];
115 		}
116 		serialno = crc32_no_comp(0, low, 8);
117 		serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
118 		snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno);
119 
120 		env_set("serial#", serialno_str);
121 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
122 	}
123 #endif
124 	return ret;
125 }
126 
127 #if defined(CONFIG_USB_FUNCTION_FASTBOOT)
128 int fb_set_reboot_flag(void)
129 {
130 	printf("Setting reboot to fastboot flag ...\n");
131 	/* Set boot mode to fastboot */
132 	writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
133 
134 	return 0;
135 }
136 #endif
137 
138 __weak int rk_board_init(void)
139 {
140 	return 0;
141 }
142 
143 __weak int rk_board_late_init(void)
144 {
145 	return 0;
146 }
147 
148 __weak int soc_clk_dump(void)
149 {
150 	return 0;
151 }
152 
153 __weak int set_armclk_rate(void)
154 {
155 	return 0;
156 }
157 
158 int board_late_init(void)
159 {
160 	rockchip_set_ethaddr();
161 	rockchip_set_serialno();
162 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0)
163 	setup_boot_mode();
164 #endif
165 
166 #ifdef CONFIG_DM_CHARGE_DISPLAY
167 	charge_display();
168 #endif
169 
170 #ifdef CONFIG_DRM_ROCKCHIP
171 	rockchip_show_logo();
172 #endif
173 
174 	soc_clk_dump();
175 
176 	return rk_board_late_init();
177 }
178 
179 #ifdef CONFIG_USING_KERNEL_DTB
180 #include <asm/arch/resource_img.h>
181 
182 int init_kernel_dtb(void)
183 {
184 	int ret = 0;
185 	ulong fdt_addr = 0;
186 
187 	fdt_addr = env_get_ulong("fdt_addr_r", 16, 0);
188 	if (!fdt_addr) {
189 		printf("No Found FDT Load Address.\n");
190 		return -1;
191 	}
192 
193 	ret = rockchip_read_dtb_file((void *)fdt_addr);
194 	if (ret < 0) {
195 		printf("%s dtb in resource read fail\n", __func__);
196 		return 0;
197 	}
198 
199 	of_live_build((void *)fdt_addr, (struct device_node **)&gd->of_root);
200 
201 	dm_scan_fdt((void *)fdt_addr, false);
202 
203 	gd->fdt_blob = (void *)fdt_addr;
204 
205 	/* Reserve 'reserved-memory' */
206 	ret = boot_fdt_add_sysmem_rsv_regions((void *)gd->fdt_blob);
207 	if (ret)
208 		return ret;
209 
210 	return 0;
211 }
212 #endif
213 
214 void board_env_fixup(void)
215 {
216 	ulong kernel_addr_r;
217 
218 	if (gd->flags & GD_FLG_BL32_ENABLED)
219 		return;
220 
221 	/* If bl32 is disabled, maybe kernel can be load to lower address. */
222 	kernel_addr_r = env_get_ulong("kernel_addr_no_bl32_r", 16, -1);
223 	if (kernel_addr_r != -1)
224 		env_set_hex("kernel_addr_r", kernel_addr_r);
225 }
226 
227 static void early_bootrom_download(void)
228 {
229 	if (!tstc())
230 		return;
231 
232 	gd->console_evt = getc();
233 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0)
234 	/* ctrl+b */
235 	if (is_hotkey(HK_BROM_DNL)) {
236 		printf("Enter bootrom download...");
237 		flushc();
238 		writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
239 		do_reset(NULL, 0, 0, NULL);
240 		printf("failed!\n");
241 	}
242 #endif
243 }
244 
245 int board_init(void)
246 {
247 	int ret;
248 
249 	board_debug_uart_init();
250 	early_bootrom_download();
251 
252 #ifdef CONFIG_USING_KERNEL_DTB
253 	init_kernel_dtb();
254 #endif
255 	/*
256 	 * pmucru isn't referenced on some platforms, so pmucru driver can't
257 	 * probe that the "assigned-clocks" is unused.
258 	 */
259 	clks_probe();
260 #ifdef CONFIG_DM_REGULATOR
261 	ret = regulators_enable_boot_on(false);
262 	if (ret)
263 		debug("%s: Cannot enable boot on regulator\n", __func__);
264 #endif
265 
266 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN
267 	io_domain_init();
268 #endif
269 
270 	set_armclk_rate();
271 
272 #ifdef CONFIG_DM_DVFS
273 	dvfs_init(true);
274 #endif
275 
276 	return rk_board_init();
277 }
278 
279 int interrupt_debugger_init(void)
280 {
281 	int ret = 0;
282 
283 #ifdef CONFIG_ROCKCHIP_DEBUGGER
284 	ret = rockchip_debugger_init();
285 #endif
286 	return ret;
287 }
288 
289 #if defined(CONFIG_ROCKCHIP_RK1808) && !defined(CONFIG_COPROCESSOR_RK1808)
290 #define PINCTRL_EMMC_BUS8_PATH		"/pinctrl/emmc/emmc-bus8"
291 #define PINCTRL_EMMC_CMD_PATH		"/pinctrl/emmc/emmc-cmd"
292 #define PINCTRL_EMMC_CLK_PATH		"/pinctrl/emmc/emmc-clk"
293 #define PINCTRL_PCFG_PU_2MA_PATH	"/pinctrl/pcfg-pull-up-2ma"
294 #define MAX_ROCKCHIP_PINS_ENTRIES	12
295 
296 static int rockchip_pinctrl_cfg_fdt_fixup(const char *path, u32 new_phandle)
297 {
298 	u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4];
299 	const u32 *data;
300 	int i, count;
301 	int node;
302 
303 	node = fdt_path_offset(gd->fdt_blob, path);
304 	if (node < 0) {
305 		debug("%s: can't find: %s\n", __func__, path);
306 		return node;
307 	}
308 
309 	data = fdt_getprop(gd->fdt_blob, node, "rockchip,pins", &count);
310 	if (!data) {
311 		debug("%s: can't find prop \"rockchip,pins\"\n", __func__);
312 		return -ENODATA;
313 	}
314 
315 	count /= sizeof(u32);
316 	if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) {
317 		debug("%s: %d is over max count\n", __func__, count);
318 		return -EINVAL;
319 	}
320 
321 	for (i = 0; i < count; i++)
322 		cells[i] = data[i];
323 
324 	for (i = 0; i < (count >> 2); i++)
325 		cells[4 * i + 3] = cpu_to_fdt32(new_phandle);
326 
327 	fdt_setprop((void *)gd->fdt_blob, node, "rockchip,pins",
328 		    &cells, count * sizeof(u32));
329 
330 	return 0;
331 }
332 #endif
333 
334 int board_fdt_fixup(void *blob)
335 {
336 	int ret = 0;
337 
338 	/*
339 	 * Common fixup for DRM
340 	 */
341 #ifdef CONFIG_DRM_ROCKCHIP
342 	rockchip_display_fixup(blob);
343 #endif
344 
345 	/*
346 	 * Platform fixup:
347 	 *
348 	 * - RK3288: Recognize RK3288W by HDMI Revision ID is 0x1A;
349 	 * - RK1808: MMC strength 2mA;
350 	 */
351 #ifdef CONFIG_ROCKCHIP_RK3288
352 	if (readl(0xff980004) == 0x1A) {
353 		ret = fdt_setprop_string(blob, 0,
354 					 "compatible", "rockchip,rk3288w");
355 		if (ret)
356 			printf("fdt set compatible failed: %d\n", ret);
357 	}
358 #elif defined(CONFIG_ROCKCHIP_RK1808) && !defined(CONFIG_COPROCESSOR_RK1808)
359 	struct tag *t;
360 	u32 ph_pu_2ma;
361 
362 	t = atags_get_tag(ATAG_SOC_INFO);
363 	if (!t)
364 		return 0;
365 
366 	debug("soc=0x%x, flags=0x%x\n", t->u.soc.name, t->u.soc.flags);
367 
368 	if (t->u.soc.flags != SOC_FLAGS_ET00)
369 		return 0;
370 
371 	ph_pu_2ma = fdt_get_phandle(gd->fdt_blob,
372 		    fdt_path_offset(gd->fdt_blob, PINCTRL_PCFG_PU_2MA_PATH));
373 	if (!ph_pu_2ma) {
374 		debug("Can't find: %s\n", PINCTRL_PCFG_PU_2MA_PATH);
375 		return -EINVAL;
376 	}
377 
378 	ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_BUS8_PATH, ph_pu_2ma);
379 	ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_CMD_PATH, ph_pu_2ma);
380 	ret |= rockchip_pinctrl_cfg_fdt_fixup(PINCTRL_EMMC_CLK_PATH, ph_pu_2ma);
381 #endif
382 
383 	return ret;
384 }
385 
386 #ifdef CONFIG_ARM64_BOOT_AARCH32
387 /*
388  * Fixup MMU region attr for OP-TEE on ARMv8 CPU:
389  *
390  * What ever U-Boot is 64-bit or 32-bit mode, the OP-TEE is always 64-bit mode.
391  *
392  * Command for OP-TEE:
393  *	64-bit mode: dcache is always enabled;
394  *	32-bit mode: dcache is always disabled(Due to some unknown issue);
395  *
396  * Command for U-Boot:
397  *	64-bit mode: MMU table is static defined in rkxxx.c file, all memory
398  *		     regions are mapped. That's good to match OP-TEE MMU policy.
399  *
400  *	32-bit mode: MMU table is setup according to gd->bd->bi_dram[..] where
401  *		     the OP-TEE region has been reserved, so it can not be
402  *		     mapped(i.e. dcache is disabled). That's also good to match
403  *		     OP-TEE MMU policy.
404  *
405  * For the data coherence when communication between U-Boot and OP-TEE, U-Boot
406  * should follow OP-TEE MMU policy.
407  *
408  * Here is the special:
409  *	When CONFIG_ARM64_BOOT_AARCH32 is enabled, U-Boot is 32-bit mode while
410  *	OP-TEE is still 64-bit mode. U-Boot would not map MMU table for OP-TEE
411  *	region(but OP-TEE requires it cacheable) so we fixup here.
412  */
413 int board_initr_caches_fixup(void)
414 {
415 	struct memblock mem;
416 
417 	mem = param_parse_optee_mem();
418 	if (mem.size)
419 		mmu_set_region_dcache_behaviour(mem.base, mem.size,
420 						DCACHE_WRITEBACK);
421 	return 0;
422 }
423 #endif
424 
425 void board_quiesce_devices(void)
426 {
427 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
428 	/* Destroy atags makes next warm boot safer */
429 	atags_destroy();
430 #endif
431 }
432 
433 void enable_caches(void)
434 {
435 	icache_enable();
436 	dcache_enable();
437 }
438 
439 #ifdef CONFIG_LMB
440 /*
441  * Using last bi_dram[...] to initialize "bootm_low" and "bootm_mapsize".
442  * This makes lmb_alloc_base() always alloc from tail of sdram.
443  * If we don't assign it, bi_dram[0] is used by default and it may cause
444  * lmb_alloc_base() fail when bi_dram[0] range is small.
445  */
446 void board_lmb_reserve(struct lmb *lmb)
447 {
448 	u64 start, size;
449 	char bootm_low[32];
450 	char bootm_mapsize[32];
451 	int i;
452 
453 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
454 		if (!gd->bd->bi_dram[i].size)
455 			break;
456 	}
457 
458 	start = gd->bd->bi_dram[i - 1].start;
459 	size = gd->bd->bi_dram[i - 1].size;
460 
461 	/*
462 	 * 32-bit kernel: ramdisk/fdt shouldn't be loaded to highmem area(768MB+),
463 	 * otherwise "Unable to handle kernel paging request at virtual address ...".
464 	 *
465 	 * So that we hope limit highest address at 768M, but there comes the the
466 	 * problem: ramdisk is a compressed image and it expands after descompress,
467 	 * so it accesses 768MB+ and brings the above "Unable to handle kernel ...".
468 	 *
469 	 * We make a appointment that the highest memory address is 512MB, it
470 	 * makes lmb alloc safer.
471 	 */
472 #ifndef CONFIG_ARM64
473 	if (start >= ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) {
474 		start = gd->bd->bi_dram[i - 2].start;
475 		size = gd->bd->bi_dram[i - 2].size;
476 	}
477 
478 	if ((start + size) > ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M))
479 		size = (u64)CONFIG_SYS_SDRAM_BASE + SZ_512M - start;
480 #endif
481 	sprintf(bootm_low, "0x%llx", start);
482 	sprintf(bootm_mapsize, "0x%llx", size);
483 	env_set("bootm_low", bootm_low);
484 	env_set("bootm_mapsize", bootm_mapsize);
485 }
486 #endif
487 
488 #ifdef CONFIG_BIDRAM
489 int board_bidram_reserve(struct bidram *bidram)
490 {
491 	struct memblock mem;
492 	int ret;
493 
494 	/* ATF */
495 	mem = param_parse_atf_mem();
496 	ret = bidram_reserve(MEMBLK_ID_ATF, mem.base, mem.size);
497 	if (ret)
498 		return ret;
499 
500 	/* PSTORE/ATAGS/SHM */
501 	mem = param_parse_common_resv_mem();
502 	ret = bidram_reserve(MEMBLK_ID_SHM, mem.base, mem.size);
503 	if (ret)
504 		return ret;
505 
506 	/* OP-TEE */
507 	mem = param_parse_optee_mem();
508 	ret = bidram_reserve(MEMBLK_ID_OPTEE, mem.base, mem.size);
509 	if (ret)
510 		return ret;
511 
512 	return 0;
513 }
514 
515 parse_fn_t board_bidram_parse_fn(void)
516 {
517 	return param_parse_ddr_mem;
518 }
519 #endif
520 
521 #ifdef CONFIG_ROCKCHIP_AMP
522 void cpu_secondary_init_r(void)
523 {
524 	amp_cpus_on();
525 }
526 #endif
527 
528 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \
529     defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS)
530 int board_init_f_init_serial(void)
531 {
532 	struct tag *t = atags_get_tag(ATAG_SERIAL);
533 
534 	if (t) {
535 		gd->serial.using_pre_serial = t->u.serial.enable;
536 		gd->serial.addr = t->u.serial.addr;
537 		gd->serial.baudrate = t->u.serial.baudrate;
538 		gd->serial.id = t->u.serial.id;
539 
540 		debug("%s: enable=%d, addr=0x%lx, baudrate=%d, id=%d\n",
541 		      __func__, gd->serial.using_pre_serial,
542 		      gd->serial.addr, gd->serial.baudrate,
543 		      gd->serial.id);
544 	}
545 
546 	return 0;
547 }
548 #endif
549 
550 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
551 #include <fdt_support.h>
552 #include <usb.h>
553 #include <usb/dwc2_udc.h>
554 
555 static struct dwc2_plat_otg_data otg_data = {
556 	.rx_fifo_sz	= 512,
557 	.np_tx_fifo_sz	= 16,
558 	.tx_fifo_sz	= 128,
559 };
560 
561 int board_usb_init(int index, enum usb_init_type init)
562 {
563 	int node;
564 	fdt_addr_t addr;
565 	const fdt32_t *reg;
566 	const void *blob = gd->fdt_blob;
567 
568 	/* find the usb_otg node */
569 	node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2");
570 
571 retry:
572 	if (node > 0) {
573 		reg = fdt_getprop(blob, node, "reg", NULL);
574 		if (!reg)
575 			return -EINVAL;
576 
577 		addr = fdt_translate_address(blob, node, reg);
578 		if (addr == OF_BAD_ADDR) {
579 			pr_err("Not found usb_otg address\n");
580 			return -EINVAL;
581 		}
582 
583 #if defined(CONFIG_ROCKCHIP_RK3288)
584 		if (addr != 0xff580000) {
585 			node = fdt_node_offset_by_compatible(blob, node,
586 							     "snps,dwc2");
587 			goto retry;
588 		}
589 #endif
590 	} else {
591 		/*
592 		 * With kernel dtb support, rk3288 dwc2 otg node
593 		 * use the rockchip legacy dwc2 driver "dwc_otg_310"
594 		 * with the compatible "rockchip,rk3288_usb20_otg",
595 		 * and rk3368 also use the "dwc_otg_310" driver with
596 		 * the compatible "rockchip,rk3368-usb".
597 		 */
598 #if defined(CONFIG_ROCKCHIP_RK3288)
599 		node = fdt_node_offset_by_compatible(blob, -1,
600 				"rockchip,rk3288_usb20_otg");
601 #elif defined(CONFIG_ROCKCHIP_RK3368)
602 		node = fdt_node_offset_by_compatible(blob, -1,
603 				"rockchip,rk3368-usb");
604 #endif
605 		if (node > 0) {
606 			goto retry;
607 		} else {
608 			pr_err("Not found usb_otg device\n");
609 			return -ENODEV;
610 		}
611 	}
612 
613 	otg_data.regs_otg = (uintptr_t)addr;
614 
615 	return dwc2_udc_probe(&otg_data);
616 }
617 
618 int board_usb_cleanup(int index, enum usb_init_type init)
619 {
620 	return 0;
621 }
622 #endif
623