1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <amp.h> 9 #include <bidram.h> 10 #include <boot_rkimg.h> 11 #include <cli.h> 12 #include <clk.h> 13 #include <console.h> 14 #include <debug_uart.h> 15 #include <dm.h> 16 #include <dvfs.h> 17 #include <io-domain.h> 18 #include <key.h> 19 #include <memblk.h> 20 #include <misc.h> 21 #include <of_live.h> 22 #include <ram.h> 23 #include <rockchip_debugger.h> 24 #include <syscon.h> 25 #include <sysmem.h> 26 #include <video_rockchip.h> 27 #include <asm/io.h> 28 #include <asm/gpio.h> 29 #include <dm/uclass-internal.h> 30 #include <dm/root.h> 31 #include <power/charge_display.h> 32 #include <power/regulator.h> 33 #include <asm/arch/boot_mode.h> 34 #include <asm/arch/clock.h> 35 #include <asm/arch/cpu.h> 36 #include <asm/arch/hotkey.h> 37 #include <asm/arch/param.h> 38 #include <asm/arch/periph.h> 39 #include <asm/arch/resource_img.h> 40 #include <asm/arch/rk_atags.h> 41 #include <asm/arch/vendor.h> 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 __weak int rk_board_late_init(void) 46 { 47 return 0; 48 } 49 50 __weak int rk_board_fdt_fixup(void *blob) 51 { 52 return 0; 53 } 54 55 __weak int soc_clk_dump(void) 56 { 57 return 0; 58 } 59 60 __weak int set_armclk_rate(void) 61 { 62 return 0; 63 } 64 65 __weak int rk_board_init(void) 66 { 67 return 0; 68 } 69 70 /* 71 * define serialno max length, the max length is 512 Bytes 72 * The remaining bytes are used to ensure that the first 512 bytes 73 * are valid when executing 'env_set("serial#", value)'. 74 */ 75 #define VENDOR_SN_MAX 513 76 #define CPUID_LEN 0x10 77 #define CPUID_OFF 0x07 78 79 static int rockchip_set_ethaddr(void) 80 { 81 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 82 char buf[ARP_HLEN_ASCII + 1]; 83 u8 ethaddr[ARP_HLEN]; 84 int ret; 85 86 ret = vendor_storage_read(VENDOR_LAN_MAC_ID, ethaddr, sizeof(ethaddr)); 87 if (ret > 0 && is_valid_ethaddr(ethaddr)) { 88 sprintf(buf, "%pM", ethaddr); 89 env_set("ethaddr", buf); 90 } 91 #endif 92 return 0; 93 } 94 95 static int rockchip_set_serialno(void) 96 { 97 u8 low[CPUID_LEN / 2], high[CPUID_LEN / 2]; 98 u8 cpuid[CPUID_LEN] = {0}; 99 char serialno_str[VENDOR_SN_MAX]; 100 int ret = 0, i; 101 u64 serialno; 102 103 /* Read serial number from vendor storage part */ 104 memset(serialno_str, 0, VENDOR_SN_MAX); 105 106 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 107 ret = vendor_storage_read(VENDOR_SN_ID, serialno_str, (VENDOR_SN_MAX-1)); 108 if (ret > 0) { 109 env_set("serial#", serialno_str); 110 } else { 111 #endif 112 #ifdef CONFIG_ROCKCHIP_EFUSE 113 struct udevice *dev; 114 115 /* retrieve the device */ 116 ret = uclass_get_device_by_driver(UCLASS_MISC, 117 DM_GET_DRIVER(rockchip_efuse), 118 &dev); 119 if (ret) { 120 printf("%s: could not find efuse device\n", __func__); 121 return ret; 122 } 123 124 /* read the cpu_id range from the efuses */ 125 ret = misc_read(dev, CPUID_OFF, &cpuid, sizeof(cpuid)); 126 if (ret) { 127 printf("%s: read cpuid from efuses failed, ret=%d\n", 128 __func__, ret); 129 return ret; 130 } 131 #else 132 /* generate random cpuid */ 133 for (i = 0; i < CPUID_LEN; i++) 134 cpuid[i] = (u8)(rand()); 135 #endif 136 /* Generate the serial number based on CPU ID */ 137 for (i = 0; i < 8; i++) { 138 low[i] = cpuid[1 + (i << 1)]; 139 high[i] = cpuid[i << 1]; 140 } 141 142 serialno = crc32_no_comp(0, low, 8); 143 serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; 144 snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno); 145 146 env_set("serial#", serialno_str); 147 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 148 } 149 #endif 150 151 return ret; 152 } 153 154 #if defined(CONFIG_USB_FUNCTION_FASTBOOT) 155 int fb_set_reboot_flag(void) 156 { 157 printf("Setting reboot to fastboot flag ...\n"); 158 writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG); 159 160 return 0; 161 } 162 #endif 163 164 #ifdef CONFIG_ROCKCHIP_USB_BOOT 165 static int boot_from_udisk(void) 166 { 167 struct blk_desc *desc; 168 char *devtype; 169 char *devnum; 170 171 devtype = env_get("devtype"); 172 devnum = env_get("devnum"); 173 174 /* Booting priority: mmc1 > udisk */ 175 if (!strcmp(devtype, "mmc") && !strcmp(devnum, "1")) 176 return 0; 177 178 if (!run_command("usb start", -1)) { 179 desc = blk_get_devnum_by_type(IF_TYPE_USB, 0); 180 if (!desc) { 181 printf("No usb device found\n"); 182 return -ENODEV; 183 } 184 185 if (!run_command("rkimgtest usb 0", -1)) { 186 rockchip_set_bootdev(desc); 187 env_set("devtype", "usb"); 188 env_set("devnum", "0"); 189 printf("Boot from usb 0\n"); 190 } else { 191 printf("No usb dev 0 found\n"); 192 return -ENODEV; 193 } 194 } 195 196 return 0; 197 } 198 #endif 199 200 static void env_fixup(void) 201 { 202 struct memblock mem; 203 ulong u_addr_r; 204 phys_size_t end; 205 char *addr_r; 206 207 #ifdef ENV_MEM_LAYOUT_SETTINGS1 208 const char *env_addr0[] = { 209 "scriptaddr", "pxefile_addr_r", 210 "fdt_addr_r", "kernel_addr_r", "ramdisk_addr_r", 211 }; 212 const char *env_addr1[] = { 213 "scriptaddr1", "pxefile_addr1_r", 214 "fdt_addr1_r", "kernel_addr1_r", "ramdisk_addr1_r", 215 }; 216 int i; 217 218 /* 128M is a typical ram size for most platform, so as default here */ 219 if (gd->ram_size <= SZ_128M) { 220 /* Replace orignal xxx_addr_r */ 221 for (i = 0; i < ARRAY_SIZE(env_addr1); i++) { 222 addr_r = env_get(env_addr1[i]); 223 if (addr_r) 224 env_set(env_addr0[i], addr_r); 225 } 226 } 227 #endif 228 /* If bl32 is disabled, maybe kernel can be load to lower address. */ 229 if (!(gd->flags & GD_FLG_BL32_ENABLED)) { 230 addr_r = env_get("kernel_addr_no_bl32_r"); 231 if (addr_r) 232 env_set("kernel_addr_r", addr_r); 233 /* If bl32 is enlarged, we move ramdisk addr right behind it */ 234 } else { 235 mem = param_parse_optee_mem(); 236 end = mem.base + mem.size; 237 u_addr_r = env_get_ulong("ramdisk_addr_r", 16, 0); 238 if (u_addr_r >= mem.base && u_addr_r < end) 239 env_set_hex("ramdisk_addr_r", end); 240 } 241 } 242 243 static void cmdline_handle(void) 244 { 245 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 246 struct tag *t; 247 248 t = atags_get_tag(ATAG_PUB_KEY); 249 if (t) { 250 /* Pass if efuse/otp programmed */ 251 if (t->u.pub_key.flag == PUBKEY_FUSE_PROGRAMMED) 252 env_update("bootargs", "fuse.programmed=1"); 253 else 254 env_update("bootargs", "fuse.programmed=0"); 255 } 256 #endif 257 } 258 259 int board_late_init(void) 260 { 261 rockchip_set_ethaddr(); 262 rockchip_set_serialno(); 263 setup_download_mode(); 264 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 265 setup_boot_mode(); 266 #endif 267 #ifdef CONFIG_ROCKCHIP_USB_BOOT 268 boot_from_udisk(); 269 #endif 270 #ifdef CONFIG_DM_CHARGE_DISPLAY 271 charge_display(); 272 #endif 273 #ifdef CONFIG_DRM_ROCKCHIP 274 rockchip_show_logo(); 275 #endif 276 env_fixup(); 277 soc_clk_dump(); 278 cmdline_handle(); 279 280 return rk_board_late_init(); 281 } 282 283 static void early_download(void) 284 { 285 #if defined(CONFIG_PWRKEY_DNL_TRIGGER_NUM) && \ 286 (CONFIG_PWRKEY_DNL_TRIGGER_NUM > 0) 287 if (pwrkey_download_init()) 288 printf("Pwrkey download init failed\n"); 289 #endif 290 291 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 292 if (is_hotkey(HK_BROM_DNL)) { 293 printf("Enter bootrom download..."); 294 flushc(); 295 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 296 do_reset(NULL, 0, 0, NULL); 297 printf("failed!\n"); 298 } 299 #endif 300 } 301 302 static void board_debug_init(void) 303 { 304 if (!gd->serial.using_pre_serial) 305 board_debug_uart_init(); 306 307 if (tstc()) { 308 gd->console_evt = getc(); 309 if (gd->console_evt <= 0x1a) /* 'z' */ 310 printf("Hotkey: ctrl+%c\n", gd->console_evt + 'a' - 1); 311 } 312 } 313 314 int board_init(void) 315 { 316 board_debug_init(); 317 318 #ifdef DEBUG 319 soc_clk_dump(); 320 #endif 321 322 #ifdef CONFIG_USING_KERNEL_DTB 323 init_kernel_dtb(); 324 #endif 325 early_download(); 326 327 /* 328 * pmucru isn't referenced on some platforms, so pmucru driver can't 329 * probe that the "assigned-clocks" is unused. 330 */ 331 clks_probe(); 332 #ifdef CONFIG_DM_REGULATOR 333 if (regulators_enable_boot_on(is_hotkey(HK_REGULATOR))) 334 debug("%s: Can't enable boot on regulator\n", __func__); 335 #endif 336 337 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN 338 io_domain_init(); 339 #endif 340 341 set_armclk_rate(); 342 343 #ifdef CONFIG_DM_DVFS 344 dvfs_init(true); 345 #endif 346 347 return rk_board_init(); 348 } 349 350 int interrupt_debugger_init(void) 351 { 352 #ifdef CONFIG_ROCKCHIP_DEBUGGER 353 return rockchip_debugger_init(); 354 #else 355 return 0; 356 #endif 357 } 358 359 int board_fdt_fixup(void *blob) 360 { 361 /* Common fixup for DRM */ 362 #ifdef CONFIG_DRM_ROCKCHIP 363 rockchip_display_fixup(blob); 364 #endif 365 366 return rk_board_fdt_fixup(blob); 367 } 368 369 #ifdef CONFIG_ARM64_BOOT_AARCH32 370 /* 371 * Fixup MMU region attr for OP-TEE on ARMv8 CPU: 372 * 373 * What ever U-Boot is 64-bit or 32-bit mode, the OP-TEE is always 64-bit mode. 374 * 375 * Command for OP-TEE: 376 * 64-bit mode: dcache is always enabled; 377 * 32-bit mode: dcache is always disabled(Due to some unknown issue); 378 * 379 * Command for U-Boot: 380 * 64-bit mode: MMU table is static defined in rkxxx.c file, all memory 381 * regions are mapped. That's good to match OP-TEE MMU policy. 382 * 383 * 32-bit mode: MMU table is setup according to gd->bd->bi_dram[..] where 384 * the OP-TEE region has been reserved, so it can not be 385 * mapped(i.e. dcache is disabled). That's also good to match 386 * OP-TEE MMU policy. 387 * 388 * For the data coherence when communication between U-Boot and OP-TEE, U-Boot 389 * should follow OP-TEE MMU policy. 390 * 391 * Here is the special: 392 * When CONFIG_ARM64_BOOT_AARCH32 is enabled, U-Boot is 32-bit mode while 393 * OP-TEE is still 64-bit mode. U-Boot would not map MMU table for OP-TEE 394 * region(but OP-TEE requires it cacheable) so we fixup here. 395 */ 396 int board_initr_caches_fixup(void) 397 { 398 struct memblock mem; 399 400 mem = param_parse_optee_mem(); 401 if (mem.size) 402 mmu_set_region_dcache_behaviour(mem.base, mem.size, 403 DCACHE_WRITEBACK); 404 return 0; 405 } 406 #endif 407 408 void arch_preboot_os(uint32_t bootm_state) 409 { 410 if (bootm_state & BOOTM_STATE_OS_PREP) 411 hotkey_run(HK_CLI_OS_PRE); 412 } 413 414 void board_quiesce_devices(void) 415 { 416 hotkey_run(HK_CMDLINE); 417 hotkey_run(HK_CLI_OS_GO); 418 419 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 420 /* Destroy atags makes next warm boot safer */ 421 atags_destroy(); 422 #endif 423 424 #if defined(CONFIG_CONSOLE_RECORD) 425 /* Print record console data */ 426 console_record_print_purge(); 427 #endif 428 } 429 430 void enable_caches(void) 431 { 432 icache_enable(); 433 dcache_enable(); 434 } 435 436 #ifdef CONFIG_LMB 437 /* 438 * Using last bi_dram[...] to initialize "bootm_low" and "bootm_mapsize". 439 * This makes lmb_alloc_base() always alloc from tail of sdram. 440 * If we don't assign it, bi_dram[0] is used by default and it may cause 441 * lmb_alloc_base() fail when bi_dram[0] range is small. 442 */ 443 void board_lmb_reserve(struct lmb *lmb) 444 { 445 char bootm_mapsize[32]; 446 char bootm_low[32]; 447 u64 start, size; 448 int i; 449 450 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 451 if (!gd->bd->bi_dram[i].size) 452 break; 453 } 454 455 start = gd->bd->bi_dram[i - 1].start; 456 size = gd->bd->bi_dram[i - 1].size; 457 458 /* 459 * 32-bit kernel: ramdisk/fdt shouldn't be loaded to highmem area(768MB+), 460 * otherwise "Unable to handle kernel paging request at virtual address ...". 461 * 462 * So that we hope limit highest address at 768M, but there comes the the 463 * problem: ramdisk is a compressed image and it expands after descompress, 464 * so it accesses 768MB+ and brings the above "Unable to handle kernel ...". 465 * 466 * We make a appointment that the highest memory address is 512MB, it 467 * makes lmb alloc safer. 468 */ 469 #ifndef CONFIG_ARM64 470 if (start >= ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) { 471 start = gd->bd->bi_dram[i - 2].start; 472 size = gd->bd->bi_dram[i - 2].size; 473 } 474 475 if ((start + size) > ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) 476 size = (u64)CONFIG_SYS_SDRAM_BASE + SZ_512M - start; 477 #endif 478 sprintf(bootm_low, "0x%llx", start); 479 sprintf(bootm_mapsize, "0x%llx", size); 480 env_set("bootm_low", bootm_low); 481 env_set("bootm_mapsize", bootm_mapsize); 482 } 483 #endif 484 485 #ifdef CONFIG_BIDRAM 486 int board_bidram_reserve(struct bidram *bidram) 487 { 488 struct memblock mem; 489 int ret; 490 491 /* ATF */ 492 mem = param_parse_atf_mem(); 493 ret = bidram_reserve(MEM_ATF, mem.base, mem.size); 494 if (ret) 495 return ret; 496 497 /* PSTORE/ATAGS/SHM */ 498 mem = param_parse_common_resv_mem(); 499 ret = bidram_reserve(MEM_SHM, mem.base, mem.size); 500 if (ret) 501 return ret; 502 503 /* OP-TEE */ 504 mem = param_parse_optee_mem(); 505 ret = bidram_reserve(MEM_OPTEE, mem.base, mem.size); 506 if (ret) 507 return ret; 508 509 return 0; 510 } 511 512 parse_fn_t board_bidram_parse_fn(void) 513 { 514 return param_parse_ddr_mem; 515 } 516 #endif 517 518 #ifdef CONFIG_ROCKCHIP_AMP 519 void cpu_secondary_init_r(void) 520 { 521 amp_cpus_on(); 522 } 523 #endif 524 525 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \ 526 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS) 527 int board_init_f_init_serial(void) 528 { 529 struct tag *t = atags_get_tag(ATAG_SERIAL); 530 531 if (t) { 532 gd->serial.using_pre_serial = t->u.serial.enable; 533 gd->serial.addr = t->u.serial.addr; 534 gd->serial.baudrate = t->u.serial.baudrate; 535 gd->serial.id = t->u.serial.id; 536 537 debug("%s: enable=%d, addr=0x%lx, baudrate=%d, id=%d\n", 538 __func__, gd->serial.using_pre_serial, 539 gd->serial.addr, gd->serial.baudrate, 540 gd->serial.id); 541 } 542 543 return 0; 544 } 545 #endif 546 547 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) 548 #include <fdt_support.h> 549 #include <usb.h> 550 #include <usb/dwc2_udc.h> 551 552 static struct dwc2_plat_otg_data otg_data = { 553 .rx_fifo_sz = 512, 554 .np_tx_fifo_sz = 16, 555 .tx_fifo_sz = 128, 556 }; 557 558 int board_usb_init(int index, enum usb_init_type init) 559 { 560 const void *blob = gd->fdt_blob; 561 const fdt32_t *reg; 562 fdt_addr_t addr; 563 int node; 564 565 /* find the usb_otg node */ 566 node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); 567 568 retry: 569 if (node > 0) { 570 reg = fdt_getprop(blob, node, "reg", NULL); 571 if (!reg) 572 return -EINVAL; 573 574 addr = fdt_translate_address(blob, node, reg); 575 if (addr == OF_BAD_ADDR) { 576 pr_err("Not found usb_otg address\n"); 577 return -EINVAL; 578 } 579 580 #if defined(CONFIG_ROCKCHIP_RK3288) 581 if (addr != 0xff580000) { 582 node = fdt_node_offset_by_compatible(blob, node, 583 "snps,dwc2"); 584 goto retry; 585 } 586 #endif 587 } else { 588 /* 589 * With kernel dtb support, rk3288 dwc2 otg node 590 * use the rockchip legacy dwc2 driver "dwc_otg_310" 591 * with the compatible "rockchip,rk3288_usb20_otg", 592 * and rk3368 also use the "dwc_otg_310" driver with 593 * the compatible "rockchip,rk3368-usb". 594 */ 595 #if defined(CONFIG_ROCKCHIP_RK3288) 596 node = fdt_node_offset_by_compatible(blob, -1, 597 "rockchip,rk3288_usb20_otg"); 598 #elif defined(CONFIG_ROCKCHIP_RK3368) 599 node = fdt_node_offset_by_compatible(blob, -1, 600 "rockchip,rk3368-usb"); 601 #endif 602 if (node > 0) { 603 goto retry; 604 } else { 605 pr_err("Not found usb_otg device\n"); 606 return -ENODEV; 607 } 608 } 609 610 otg_data.regs_otg = (uintptr_t)addr; 611 612 return dwc2_udc_probe(&otg_data); 613 } 614 615 int board_usb_cleanup(int index, enum usb_init_type init) 616 { 617 return 0; 618 } 619 #endif 620