1if ARCH_ROCKCHIP 2 3config ROCKCHIP_PX30 4 bool "Support Rockchip PX30" 5 select ARM64 6 select GICV2 7 select ARM_SMCCC 8 select SUPPORT_SPL 9 select SUPPORT_TPL 10 select SPL 11 select TPL 12 select TPL_TINY_FRAMEWORK if TPL 13 14 imply SPL_SERIAL_SUPPORT 15 imply TPL_SERIAL_SUPPORT 16 select DEBUG_UART_BOARD_INIT 17 help 18 The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35 19 including NEON and GPU, Mali-400 graphics, several DDR3 options 20 and video codec support. Peripherals include Gigabit Ethernet, 21 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. 22 23if ROCKCHIP_PX30 24 25config TPL_LDSCRIPT 26 default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" 27 28config TPL_TEXT_BASE 29 default 0xff0e1000 30 31config TPL_MAX_SIZE 32 default 10240 33 34config ROCKCHIP_RK3326 35 bool "Support Rockchip RK3326 " 36 help 37 RK3326 can use most code from PX30, but at some situations we have 38 to distinguish between RK3326 and PX30, so this macro gives help. 39 It is usually selected in rk3326 board defconfig. 40endif 41 42config ROCKCHIP_RK3036 43 bool "Support Rockchip RK3036" 44 select CPU_V7 45 select SUPPORT_SPL 46 select SUPPORT_TPL 47 select SPL 48 select TPL 49 select BOARD_LATE_INIT 50 select ROCKCHIP_BROM_HELPER 51 select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL 52 select TPL_NEEDS_SEPARATE_STACK if TPL 53 select DEBUG_UART_BOARD_INIT 54 select ARM_SMCCC 55 help 56 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 57 including NEON and GPU, Mali-400 graphics, several DDR3 options 58 and video codec support. Peripherals include Gigabit Ethernet, 59 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. 60 61config ROCKCHIP_RK3128 62 bool "Support Rockchip RK3128" 63 select CPU_V7 64 select GICV2 65 select ARM_SMCCC 66 help 67 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7 68 including NEON and GPU, Mali-400 graphics, several DDR3 options 69 and video codec support. Peripherals include Gigabit Ethernet, 70 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. 71 72if ROCKCHIP_RK3128 73 74config ROCKCHIP_RK3126 75 bool "Support Rockchip RK3126 " 76 help 77 RK3126 can use most code from RK3128, but at some situations we have 78 to distinguish between RK3126 and RK3128, so this macro gives help. 79 It is usually selected in rk3126 board defconfig. 80 81config ROCKCHIP_PX3SE 82 bool "Support Rockchip PX3SE" 83 help 84 PX3SE is a variant of RK3128, it shares codes with RK3128, but we still 85 need this macro to distinguish PX3SE and RK3128. 86endif 87 88config ROCKCHIP_RK3066 89 bool "Support Rockchip RK3066" 90 select CPU_V7 91 select SUPPORT_SPL 92 select SUPPORT_TPL 93 select SPL 94 select TPL 95 select BOARD_LATE_INIT 96 select ROCKCHIP_BROM_HELPER 97 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM 98 help 99 The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9 100 including NEON and GPU, Mali-400 graphics, several DDR3 options 101 and video codec support. Peripherals include ethernet, USB2 host 102 and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. 103 104config ROCKCHIP_RK3188 105 bool "Support Rockchip RK3188" 106 select CPU_V7 107 select SPL_BOARD_INIT if SPL 108 select SUPPORT_SPL 109 select SPL 110 select SPL_CLK 111 select SPL_REGMAP 112 select SPL_SYSCON 113 select SPL_RAM 114 select SPL_DRIVERS_MISC_SUPPORT 115 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM 116 select BOARD_LATE_INIT 117 select ROCKCHIP_BROM_HELPER 118 help 119 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9 120 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two 121 video interfaces, several memory options and video codec support. 122 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S, 123 UART, SPI, I2C and PWMs. 124 125config ROCKCHIP_RK322X 126 bool "Support Rockchip RK3228/RK3229" 127 select CPU_V7 128 select SUPPORT_SPL 129 select SUPPORT_TPL 130 select SPL 131 select TPL 132 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL 133 select TPL_NEEDS_SEPARATE_STACK if TPL 134 select SPL_DRIVERS_MISC_SUPPORT 135 imply SPL_SERIAL_SUPPORT 136 imply TPL_SERIAL_SUPPORT 137 select ROCKCHIP_BROM_HELPER 138 select DEBUG_UART_BOARD_INIT 139 select TPL_LIBCOMMON_SUPPORT 140 select TPL_LIBGENERIC_SUPPORT 141 select GICV2 142 select ARM_SMCCC 143 help 144 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7 145 including NEON and GPU, Mali-400 graphics, several DDR3 options 146 and video codec support. Peripherals include Gigabit Ethernet, 147 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. 148 149if ROCKCHIP_RK322X 150 151config ROCKCHIP_RK3128X 152 bool "Support Rockchip RK3128X " 153 help 154 RK3128X can use most code from RK322X, but at some situations we have 155 to distinguish between RK3128X and RK322X, so this macro gives help. 156 It is usually selected in RK3128X board defconfig. 157endif 158 159config ROCKCHIP_RK3288 160 bool "Support Rockchip RK3288" 161 select CPU_V7 162 select SPL_BOARD_INIT if SPL 163 select SUPPORT_SPL 164 select SPL 165 select GICV2 166 select ARM_SMCCC 167 help 168 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17 169 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two 170 video interfaces supporting HDMI and eDP, several DDR3 options 171 and video codec support. Peripherals include Gigabit Ethernet, 172 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. 173 174config ROCKCHIP_RK3308 175 bool "Support Rockchip RK3308" 176 select ARM64 if !ARM64_BOOT_AARCH32 177 select DEBUG_UART_BOARD_INIT 178 select ARM_SMCCC 179 help 180 The Rockchip RK3308 is a ARM-based Soc which embeded with quad 181 Cortex-A35 and highly integrated audio interfaces. 182 183config ROCKCHIP_RK3328 184 bool "Support Rockchip RK3328" 185 select ARM64 186 select GICV2 187 select SUPPORT_SPL 188 select SUPPORT_TPL 189 select SPL 190 select TPL 191 select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL 192 select TPL_NEEDS_SEPARATE_STACK if TPL 193 imply SPL_SERIAL_SUPPORT 194 imply TPL_SERIAL_SUPPORT 195 imply SPL_SEPARATE_BSS 196 select DEBUG_UART_BOARD_INIT 197 select ARM_SMCCC 198 help 199 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. 200 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two 201 video interfaces supporting HDMI and eDP, several DDR3 options 202 and video codec support. Peripherals include Gigabit Ethernet, 203 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. 204 205if ROCKCHIP_RK3328 206 207config TPL_LDSCRIPT 208 default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" 209 210config TPL_TEXT_BASE 211 default 0xff091000 212 213config TPL_MAX_SIZE 214 default 28672 215 216config TPL_STACK 217 default 0xff098000 218 219endif 220 221config ROCKCHIP_RK3368 222 bool "Support Rockchip RK3368" 223 select ARM64 224 select SUPPORT_SPL 225 select SUPPORT_TPL 226 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL 227 select TPL_NEEDS_SEPARATE_STACK if TPL 228 imply SPL_SEPARATE_BSS 229 imply SPL_SERIAL_SUPPORT 230 imply TPL_SERIAL_SUPPORT 231 select DEBUG_UART_BOARD_INIT 232 select GICV2 233 select ARM_SMCCC 234 help 235 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised 236 into a big and little cluster with 4 cores each) Cortex-A53 including 237 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache 238 (for the little cluster), PowerVR G6110 based graphics, one video 239 output processor supporting LVDS/HDMI/eDP, several DDR3 options and 240 video codec support. 241 242 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, 243 I2S, UARTs, SPI, I2C and PWMs. 244 245if ROCKCHIP_RK3368 246 247config TPL_LDSCRIPT 248 default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds" 249 250config TPL_TEXT_BASE 251 default 0xff8c1000 252 253config TPL_MAX_SIZE 254 default 28672 255 256config TPL_STACK 257 default 0xff8cffff 258 259endif 260 261config ROCKCHIP_RK3399 262 bool "Support Rockchip RK3399" 263 select ARM64 264 select SUPPORT_SPL 265 select SPL 266 select SPL_SEPARATE_BSS 267 select SPL_SERIAL_SUPPORT 268 select SPL_DRIVERS_MISC_SUPPORT 269 select DEBUG_UART_BOARD_INIT 270 select GICV3 271 select BOARD_LATE_INIT 272 select ROCKCHIP_BROM_HELPER 273 select ARM_SMCCC 274 help 275 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 276 and quad-core Cortex-A53. 277 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two 278 video interfaces supporting HDMI and eDP, several DDR3 options 279 and video codec support. Peripherals include Gigabit Ethernet, 280 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. 281 282config ROCKCHIP_RV1108 283 bool "Support Rockchip RV1108" 284 select CPU_V7 285 select SUPPORT_SPL 286 select SPL 287 select BOARD_LATE_INIT 288 help 289 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 290 and a DSP. 291 292config SPL_ROCKCHIP_BACK_TO_BROM 293 bool "SPL returns to bootrom" 294 default y if ROCKCHIP_RK3036 295 select ROCKCHIP_BROM_HELPER 296 depends on SPL 297 help 298 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, 299 SPL will return to the boot rom, which will then load the U-Boot 300 binary to keep going on. 301 302config TPL_ROCKCHIP_BACK_TO_BROM 303 bool "TPL returns to bootrom" 304 default y if ROCKCHIP_RK3368 || ROCKCHIP_RK3328 305 select ROCKCHIP_BROM_HELPER 306 depends on TPL 307 help 308 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, 309 SPL will return to the boot rom, which will then load the U-Boot 310 binary to keep going on. 311 312config ARM64_BOOT_AARCH32 313 bool "Support Boot an ARM64 on AArch32 execution state" 314 select CPU_V7 315 default n 316 help 317 If you want to boot an ARM64 processor on 32-bit mode, say y here. 318 319config ROCKCHIP_BOOT_MODE_REG 320 hex "Rockchip boot mode flag register address" 321 default 0xff010200 if ROCKCHIP_PX30 322 default 0x200081c8 if ROCKCHIP_RK3036 323 default 0x100a0038 if ROCKCHIP_RK3128 324 default 0x20004040 if ROCKCHIP_RK3188 325 default 0x110005c8 if ROCKCHIP_RK322X 326 default 0xff730094 if ROCKCHIP_RK3288 327 default 0xff000500 if ROCKCHIP_RK3308 328 default 0xff1005c8 if ROCKCHIP_RK3328 329 default 0xff738200 if ROCKCHIP_RK3368 330 default 0xff320300 if ROCKCHIP_RK3399 331 default 0x10300580 if ROCKCHIP_RV1108 332 default 0 333 help 334 The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h) 335 according to the value from this register. 336 337config ROCKCHIP_STIMER_BASE 338 hex "Rockchip Secure timer base address" 339 default 0xff220020 if ROCKCHIP_PX30 340 default 0x200440a0 if ROCKCHIP_RK3036 341 default 0x2000e000 if ROCKCHIP_RK3066 342 default 0x20018020 if ROCKCHIP_RK3126 343 default 0x200440a0 if ROCKCHIP_RK3128 344 default 0x2000e000 if ROCKCHIP_RK3188 345 default 0x110d0020 if ROCKCHIP_RK322X 346 default 0xff810020 if ROCKCHIP_RK3288 347 default 0xff1d0020 if ROCKCHIP_RK3328 348 default 0xff830020 if ROCKCHIP_RK3368 349 default 0xff8680a0 if ROCKCHIP_RK3399 350 default 0x10350020 if ROCKCHIP_RV1108 351 default 0 352 help 353 The secure timer inited in SPL/TPL in secure word, ARM generic timer 354 works after this timer work. 355 356config ROCKCHIP_IRAM_START_ADDR 357 hex "Rockchip Secure timer base address" 358 default 0xff0e0000 if ROCKCHIP_PX30 359 default 0x10080000 if ROCKCHIP_RK3036 360 default 0x10080000 if ROCKCHIP_RK3128 361 default 0x10080000 if ROCKCHIP_RK3188 362 default 0x10080000 if ROCKCHIP_RK322X 363 default 0xff700000 if ROCKCHIP_RK3288 364 default 0xfff80000 if ROCKCHIP_RK3308 365 default 0xff091000 if ROCKCHIP_RK3328 366 default 0xff8c0000 if ROCKCHIP_RK3368 367 default 0xff8c0000 if ROCKCHIP_RK3399 368 default 0x10080000 if ROCKCHIP_RV1108 369 default 0 370 help 371 The IRAM start addr is to locate variant of the boot device from 372 bootrom. 373 374config ROCKCHIP_SPL_RESERVE_IRAM 375 hex "Size of IRAM reserved in SPL" 376 default 0 377 help 378 SPL may need reserve memory for firmware loaded by SPL, whose load 379 address is in IRAM and may overlay with SPL text area if not 380 reserved. 381 382config ROCKCHIP_BROM_HELPER 383 bool 384 385config SPL_ROCKCHIP_EARLYRETURN_TO_BROM 386 bool "SPL requires early-return (for RK3188-style BROM) to BROM" 387 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK 388 help 389 Some Rockchip BROM variants (e.g. on the RK3188) load the 390 first stage in segments and enter multiple times. E.g. on 391 the RK3188, the first 1KB of the first stage are loaded 392 first and entered; after returning to the BROM, the 393 remainder of the first stage is loaded, but the BROM 394 re-enters at the same address/to the same code as previously. 395 396 This enables support code in the BOOT0 hook for the SPL stage 397 to allow multiple entries. 398 399config TPL_ROCKCHIP_EARLYRETURN_TO_BROM 400 bool "TPL requires early-return (for RK3188-style BROM) to BROM" 401 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK 402 help 403 Some Rockchip BROM variants (e.g. on the RK3188) load the 404 first stage in segments and enter multiple times. E.g. on 405 the RK3188, the first 1KB of the first stage are loaded 406 first and entered; after returning to the BROM, the 407 remainder of the first stage is loaded, but the BROM 408 re-enters at the same address/to the same code as previously. 409 410 This enables support code in the BOOT0 hook for the TPL stage 411 to allow multiple entries. 412 413config SPL_MMC_SUPPORT 414 default y if !SPL_ROCKCHIP_BACK_TO_BROM 415 416config RKIMG_BOOTLOADER 417 bool "Support for Rockchip Image Bootloader boot flow" 418 default n 419 help 420 Rockchip use this to boot Android during development cycle and for 421 other OS, typical content kernel.img with zImage/Image, boot.img and 422 recovery.img with Ramdisk, packed with 'KNRL' header; and resource.img 423 with dtb and uboot/kernel logo bmp, vendor storage for custom info 424 like SN and MAC address. 425 426config ROCKCHIP_RESOURCE_IMAGE 427 bool "Enable support for rockchip resource image" 428 depends on RKIMG_BOOTLOADER 429 default y 430 help 431 This enables support to get dtb or logo files from 432 rockchip resource image format partition. 433 434config ROCKCHIP_VENDOR_PARTITION 435 bool "Rockchip vendor storage partition support" 436 depends on RKIMG_BOOTLOADER 437 help 438 This enable support to read/write vendor configuration data from/to 439 this partition. 440 441config USING_KERNEL_DTB 442 bool "Using dtb from Kernel/resource for U-Boot" 443 depends on RKIMG_BOOTLOADER && OF_LIVE 444 default y 445 help 446 This enable support to read dtb from resource and use it for U-Boot, 447 the uart and emmc will still using U-Boot dtb, but other devices like 448 regulator/pmic, display, usb will use dts node from kernel. 449 450config ROCKCHIP_CRC 451 bool "Rockchip CRC verify images" 452 help 453 This enable support Rockchip CRC verify images. It takes a lot of time, 454 so it is better only used for debug. 455 456config ROCKCHIP_SMCCC 457 bool "Rockchip SMCCC" 458 default y if ARM_SMCCC 459 help 460 This enable support for Rockchip SMC calls 461 462config ROCKCHIP_DEBUGGER 463 bool "Rockchip debugger" 464 depends on IRQ 465 help 466 This enable support for Rockchip debugger. Now we install a timer interrupt 467 and dump pt_regs when the timeout event trigger. This helps us to know cpu 468 state when system hang. 469 470config ROCKCHIP_CRASH_DUMP 471 bool "Rockchip crash dump registers" 472 help 473 This enable dump registers when system crash, the registers you would like 474 to dump can be added in show_regs(). 475 476config GICV2 477 bool "ARM GICv2" 478 479config GICV3 480 bool "ARM GICv3" 481 482source "arch/arm/mach-rockchip/px30/Kconfig" 483source "arch/arm/mach-rockchip/rk3036/Kconfig" 484source "arch/arm/mach-rockchip/rk3066/Kconfig" 485source "arch/arm/mach-rockchip/rk3128/Kconfig" 486source "arch/arm/mach-rockchip/rk3188/Kconfig" 487source "arch/arm/mach-rockchip/rk322x/Kconfig" 488source "arch/arm/mach-rockchip/rk3288/Kconfig" 489source "arch/arm/mach-rockchip/rk3308/Kconfig" 490source "arch/arm/mach-rockchip/rk3328/Kconfig" 491source "arch/arm/mach-rockchip/rk3368/Kconfig" 492source "arch/arm/mach-rockchip/rk3399/Kconfig" 493source "arch/arm/mach-rockchip/rv1108/Kconfig" 494endif 495