xref: /rk3399_rockchip-uboot/arch/arm/mach-rockchip/Kconfig (revision 7a6ed8e85fb413a7da484e9c30b1e9beab2e594a)
1if ARCH_ROCKCHIP
2
3config ROCKCHIP_RK3036
4	bool "Support Rockchip RK3036"
5	select CPU_V7
6	select SUPPORT_SPL
7	select SPL
8	help
9	  The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
10	  including NEON and GPU, Mali-400 graphics, several DDR3 options
11	  and video codec support. Peripherals include Gigabit Ethernet,
12	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
13
14config ROCKCHIP_RK3128
15	bool "Support Rockchip RK3128"
16	select CPU_V7
17	select GICV2
18	select ARM_SMCCC
19	help
20	  The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21	  including NEON and GPU, Mali-400 graphics, several DDR3 options
22	  and video codec support. Peripherals include Gigabit Ethernet,
23	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
24
25if ROCKCHIP_RK3128
26
27config ROCKCHIP_RK3126
28	bool "Support Rockchip RK3126 "
29	help
30	  RK3126 can use most code from RK3128, but at some situations we have
31	  to distinguish between RK3126 and RK3128, so this macro gives help.
32	  It is usually selected in rk3126 board defconfig.
33endif
34
35config ROCKCHIP_RK3066
36	bool "Support Rockchip RK3066"
37	select CPU_V7
38	select SUPPORT_SPL
39	select SUPPORT_TPL
40	select SPL
41	select TPL
42	select BOARD_LATE_INIT
43	select ROCKCHIP_BROM_HELPER
44	select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
45	help
46	  The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9
47	  including NEON and GPU, Mali-400 graphics, several DDR3 options
48	  and video codec support. Peripherals include ethernet, USB2 host
49	  and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
50
51config ROCKCHIP_RK3188
52	bool "Support Rockchip RK3188"
53	select CPU_V7
54	select SPL_BOARD_INIT if SPL
55	select SUPPORT_SPL
56	select SPL
57	select SPL_CLK
58	select SPL_PINCTRL
59	select SPL_REGMAP
60	select SPL_SYSCON
61	select SPL_RAM
62	select SPL_DRIVERS_MISC_SUPPORT
63	select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
64	select BOARD_LATE_INIT
65	select ROCKCHIP_BROM_HELPER
66	help
67	  The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
68	  including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
69	  video interfaces, several memory options and video codec support.
70	  Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
71	  UART, SPI, I2C and PWMs.
72
73config ROCKCHIP_RK322X
74	bool "Support Rockchip RK3228/RK3229"
75	select CPU_V7
76	select SUPPORT_SPL
77	select SUPPORT_TPL
78	select SPL
79	select TPL
80	select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
81	select TPL_NEEDS_SEPARATE_STACK if TPL
82	select SPL_DRIVERS_MISC_SUPPORT
83	imply SPL_SERIAL_SUPPORT
84	imply TPL_SERIAL_SUPPORT
85	select ROCKCHIP_BROM_HELPER
86	select DEBUG_UART_BOARD_INIT
87	select TPL_LIBCOMMON_SUPPORT
88	select TPL_LIBGENERIC_SUPPORT
89	select GICV2
90	help
91	  The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
92	  including NEON and GPU, Mali-400 graphics, several DDR3 options
93	  and video codec support. Peripherals include Gigabit Ethernet,
94	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
95
96config ROCKCHIP_RK3288
97	bool "Support Rockchip RK3288"
98	select CPU_V7
99	select SPL_BOARD_INIT if SPL
100	select SUPPORT_SPL
101	select SPL
102	select GICV2
103	help
104	  The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
105	  including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
106	  video interfaces supporting HDMI and eDP, several DDR3 options
107	  and video codec support. Peripherals include Gigabit Ethernet,
108	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
109
110config ROCKCHIP_RK3328
111	bool "Support Rockchip RK3328"
112	select ARM64
113	select GICV2
114	select SUPPORT_SPL
115	select SUPPORT_TPL
116	select SPL
117	select TPL
118	select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
119	select TPL_NEEDS_SEPARATE_STACK if TPL
120	imply SPL_SERIAL_SUPPORT
121	imply TPL_SERIAL_SUPPORT
122	imply SPL_SEPARATE_BSS
123	select DEBUG_UART_BOARD_INIT
124	help
125	  The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
126	  including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
127	  video interfaces supporting HDMI and eDP, several DDR3 options
128	  and video codec support. Peripherals include Gigabit Ethernet,
129	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
130
131if ROCKCHIP_RK3328
132
133config TPL_LDSCRIPT
134	default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
135
136config TPL_TEXT_BASE
137        default 0xff091000
138
139config TPL_MAX_SIZE
140        default 28672
141
142config TPL_STACK
143        default 0xff098000
144
145endif
146
147config ROCKCHIP_RK3368
148	bool "Support Rockchip RK3368"
149	select ARM64
150	select SUPPORT_SPL
151	select SUPPORT_TPL
152	select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
153	select TPL_NEEDS_SEPARATE_STACK if TPL
154	imply SPL_SEPARATE_BSS
155	imply SPL_SERIAL_SUPPORT
156	imply TPL_SERIAL_SUPPORT
157	select DEBUG_UART_BOARD_INIT
158	select GICV2
159	help
160	  The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
161	  into a big and little cluster with 4 cores each) Cortex-A53 including
162	  AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
163	  (for the little cluster), PowerVR G6110 based graphics, one video
164	  output processor supporting LVDS/HDMI/eDP, several DDR3 options and
165	  video codec support.
166
167	  On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
168	  I2S, UARTs, SPI, I2C and PWMs.
169
170if ROCKCHIP_RK3368
171
172config TPL_LDSCRIPT
173	default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
174
175config TPL_TEXT_BASE
176        default 0xff8c1000
177
178config TPL_MAX_SIZE
179        default 28672
180
181config TPL_STACK
182        default 0xff8cffff
183
184endif
185
186config ROCKCHIP_RK3399
187	bool "Support Rockchip RK3399"
188	select ARM64
189	select SUPPORT_SPL
190	select SPL
191	select SPL_SEPARATE_BSS
192	select SPL_SERIAL_SUPPORT
193	select SPL_DRIVERS_MISC_SUPPORT
194	select DEBUG_UART_BOARD_INIT
195	select GICV3
196	select BOARD_LATE_INIT
197	select ROCKCHIP_BROM_HELPER
198	help
199	  The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
200	  and quad-core Cortex-A53.
201	  including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
202	  video interfaces supporting HDMI and eDP, several DDR3 options
203	  and video codec support. Peripherals include Gigabit Ethernet,
204	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
205
206config ROCKCHIP_RV1108
207	bool "Support Rockchip RV1108"
208	select CPU_V7
209	help
210	  The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
211	  and a DSP.
212
213config SPL_ROCKCHIP_BACK_TO_BROM
214	bool "SPL returns to bootrom"
215	default y if ROCKCHIP_RK3036
216	select ROCKCHIP_BROM_HELPER
217	depends on SPL
218	help
219	  Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
220          SPL will return to the boot rom, which will then load the U-Boot
221          binary to keep going on.
222
223config TPL_ROCKCHIP_BACK_TO_BROM
224	bool "TPL returns to bootrom"
225	default y if ROCKCHIP_RK3368 || ROCKCHIP_RK3328
226	select ROCKCHIP_BROM_HELPER
227	depends on TPL
228	help
229	  Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
230          SPL will return to the boot rom, which will then load the U-Boot
231          binary to keep going on.
232
233config ROCKCHIP_BOOT_MODE_REG
234	hex "Rockchip boot mode flag register address"
235	default 0x200081c8 if ROCKCHIP_RK3036
236	default 0x100a0038 if ROCKCHIP_RK3128
237	default 0x20004040 if ROCKCHIP_RK3188
238	default 0x110005c8 if ROCKCHIP_RK322X
239	default 0xff730094 if ROCKCHIP_RK3288
240	default 0xff1005c8 if ROCKCHIP_RK3328
241	default 0xff738200 if ROCKCHIP_RK3368
242	default 0xff320300 if ROCKCHIP_RK3399
243	default 0x10300580 if ROCKCHIP_RV1108
244	default 0
245	help
246	  The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h)
247	  according to the value from this register.
248
249config ROCKCHIP_STIMER_BASE
250	hex "Rockchip Secure timer base address"
251	default 0xff220020 if ROCKCHIP_PX30
252	default 0x200440a0 if ROCKCHIP_RK3036
253	default 0x2000e000 if ROCKCHIP_RK3066
254	default 0x20018020 if ROCKCHIP_RK3126
255	default 0x200440a0 if ROCKCHIP_RK3128
256	default 0x2000e000 if ROCKCHIP_RK3188
257	default 0x110d0020 if ROCKCHIP_RK322X
258	default 0xff810020 if ROCKCHIP_RK3288
259	default 0xff1d0020 if ROCKCHIP_RK3328
260	default 0xff830020 if ROCKCHIP_RK3368
261	default 0xff8680a0 if ROCKCHIP_RK3399
262	default 0x10350020 if ROCKCHIP_RV1108
263	default 0
264	help
265	  The secure timer inited in SPL/TPL in secure word, ARM generic timer
266	  works after this timer work.
267
268config ROCKCHIP_IRAM_START_ADDR
269	hex "Rockchip Secure timer base address"
270	default 0xff0e0000 if ROCKCHIP_PX30
271	default 0x10080000 if ROCKCHIP_RK3036
272	default 0x10080000 if ROCKCHIP_RK3128
273	default 0x10080000 if ROCKCHIP_RK3188
274	default 0x10080000 if ROCKCHIP_RK322X
275	default 0xff700000 if ROCKCHIP_RK3288
276	default 0xff091000 if ROCKCHIP_RK3328
277	default 0xff8c0000 if ROCKCHIP_RK3368
278	default 0xff8c0000 if ROCKCHIP_RK3399
279	default 0x10080000 if ROCKCHIP_RV1108
280	default 0
281	help
282	  The IRAM start addr is to locate variant of the boot device from
283	  bootrom.
284
285config ROCKCHIP_SPL_RESERVE_IRAM
286	hex "Size of IRAM reserved in SPL"
287	default 0
288	help
289	  SPL may need reserve memory for firmware loaded by SPL, whose load
290	  address is in IRAM and may overlay with SPL text area if not
291	  reserved.
292
293config ROCKCHIP_BROM_HELPER
294	bool
295
296config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
297        bool "SPL requires early-return (for RK3188-style BROM) to BROM"
298	depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
299	help
300	  Some Rockchip BROM variants (e.g. on the RK3188) load the
301	  first stage in segments and enter multiple times. E.g. on
302	  the RK3188, the first 1KB of the first stage are loaded
303	  first and entered; after returning to the BROM, the
304	  remainder of the first stage is loaded, but the BROM
305	  re-enters at the same address/to the same code as previously.
306
307	  This enables support code in the BOOT0 hook for the SPL stage
308	  to allow multiple entries.
309
310config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
311        bool "TPL requires early-return (for RK3188-style BROM) to BROM"
312	depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
313	help
314	  Some Rockchip BROM variants (e.g. on the RK3188) load the
315	  first stage in segments and enter multiple times. E.g. on
316	  the RK3188, the first 1KB of the first stage are loaded
317	  first and entered; after returning to the BROM, the
318	  remainder of the first stage is loaded, but the BROM
319	  re-enters at the same address/to the same code as previously.
320
321	  This enables support code in the BOOT0 hook for the TPL stage
322	  to allow multiple entries.
323
324config SPL_MMC_SUPPORT
325	default y if !SPL_ROCKCHIP_BACK_TO_BROM
326
327config RKIMG_BOOTLOADER
328	bool "Support for Rockchip Image Bootloader boot flow"
329	default n
330	help
331	  Rockchip use this to boot Android during development cycle and for
332	  other OS, typical content kernel.img with zImage/Image, boot.img and
333	  recovery.img with Ramdisk, packed with 'KNRL' header; and resource.img
334	  with dtb and uboot/kernel logo bmp, vendor storage for custom info
335	  like SN and MAC address.
336
337config ROCKCHIP_RESOURCE_IMAGE
338	bool "Enable support for rockchip resource image"
339	depends on RKIMG_BOOTLOADER
340	help
341	  This enables support to get dtb or logo files from
342	  rockchip resource image format partition.
343
344config ROCKCHIP_VENDOR_PARTITION
345	bool "Rockchip vendor storage partition support"
346	depends on RKIMG_BOOTLOADER
347	help
348	  This enable support to read/write vendor configuration data from/to
349	  this partition.
350
351config ROCKCHIP_CRC
352	bool "Rockchip CRC verify images"
353	help
354	  This enable support Rockchip CRC verify images. It takes a lot of time,
355	  so it is better only used for debug.
356
357config ROCKCHIP_SMCCC
358	bool "Rockchip SMCCC"
359	default y if ARM_SMCCC
360	help
361	  This enable support for Rockchip SMC calls
362
363config GICV2
364	bool "ARM GICv2"
365
366config GICV3
367	bool "ARM GICv3"
368
369source "arch/arm/mach-rockchip/rk3036/Kconfig"
370source "arch/arm/mach-rockchip/rk3066/Kconfig"
371source "arch/arm/mach-rockchip/rk3128/Kconfig"
372source "arch/arm/mach-rockchip/rk3188/Kconfig"
373source "arch/arm/mach-rockchip/rk322x/Kconfig"
374source "arch/arm/mach-rockchip/rk3288/Kconfig"
375source "arch/arm/mach-rockchip/rk3328/Kconfig"
376source "arch/arm/mach-rockchip/rk3368/Kconfig"
377source "arch/arm/mach-rockchip/rk3399/Kconfig"
378source "arch/arm/mach-rockchip/rv1108/Kconfig"
379endif
380