1 /* 2 * arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c 3 * 4 * Copyright (C) 2013 Renesas Electronics Corporation 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #include <common.h> 10 #include <sh_pfc.h> 11 #include <asm/gpio.h> 12 #include "pfc-r8a7790.h" 13 14 enum { 15 PINMUX_RESERVED = 0, 16 17 PINMUX_DATA_BEGIN, 18 GP_ALL(DATA), 19 PINMUX_DATA_END, 20 21 PINMUX_INPUT_BEGIN, 22 GP_ALL(IN), 23 PINMUX_INPUT_END, 24 25 PINMUX_OUTPUT_BEGIN, 26 GP_ALL(OUT), 27 PINMUX_OUTPUT_END, 28 29 PINMUX_FUNCTION_BEGIN, 30 GP_ALL(FN), 31 32 /* GPSR0 */ 33 FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5, 34 FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11, 35 FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19, 36 FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29, 37 FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8, 38 FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20, 39 40 /* GPSR1 */ 41 FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3, 42 FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16, 43 FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25, 44 FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N, 45 FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18, 46 FN_IP3_21_20, 47 48 /* GPSR2 */ 49 FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, 50 FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19, 51 FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26, 52 FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9, 53 FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22, 54 FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0, 55 FN_IP6_5_3, FN_IP6_7_6, 56 57 /* GPSR3 */ 58 FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13, 59 FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24, 60 FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9, 61 FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24, 62 FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7, 63 FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16, 64 FN_IP9_18_17, 65 66 /* GPSR4 */ 67 FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25, 68 FN_VI0_DATA0_VI0_B0, FN_VI0_DATA0_VI0_B1, FN_VI0_DATA0_VI0_B2, 69 FN_IP9_28_27, FN_VI0_DATA0_VI0_B4, FN_VI0_DATA0_VI0_B5, 70 FN_VI0_DATA0_VI0_B6, FN_VI0_DATA0_VI0_B7, FN_IP9_31_29, FN_IP10_2_0, 71 FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15, 72 FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25, 73 FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6, 74 FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4, 75 76 /* GPSR5 */ 77 FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19, 78 FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24, 79 FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30, 80 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10, 81 FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20, 82 FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3, 83 FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22, 84 85 /* GPSR6 */ 86 FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14, 87 FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, FN_IP13_22, FN_IP13_24_23, 88 FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0, 89 FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7, 90 FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17, 91 FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29, 92 93 /* GPSR7 */ 94 FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24, 95 FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8, 96 FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, 97 FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27, 98 FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12, 99 FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, 100 101 /* IPSR0 - IPSR10 */ 102 103 /* IPSR11 */ 104 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D, 105 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B, 106 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, 107 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 108 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B, 109 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B, 110 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 111 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 112 FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5, 113 FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7, 114 FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO, 115 FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC, 116 FN_VI1_DATA7, FN_AVB_MDC, 117 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 118 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 119 120 /* IPSR12 */ 121 FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, 122 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7, 123 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, 124 FN_SCL2_D, FN_MSIOF1_RXD_E, 125 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E, 126 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, 127 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, 128 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, 129 FN_CAN1_TX_C, FN_MSIOF1_TXD_E, 130 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, 131 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 132 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 133 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 134 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, 135 FN_ADIDATA_B, FN_MSIOF0_SYNC_C, 136 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, 137 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, 138 139 /* IPSR13 */ 140 /* MOD_SEL */ 141 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 142 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, 143 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, 144 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, 145 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 146 FN_SEL_SSI9_0, FN_SEL_SSI9_1, 147 FN_SEL_SCFA_0, FN_SEL_SCFA_1, 148 FN_SEL_QSP_0, FN_SEL_QSP_1, 149 FN_SEL_SSI7_0, FN_SEL_SSI7_1, 150 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3, 151 FN_SEL_HSCIF1_4, 152 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 153 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 154 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, 155 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 156 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 157 158 /* MOD_SEL2 */ 159 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, 160 FN_SEL_SCIF0_4, 161 FN_SEL_SCIF_0, FN_SEL_SCIF_1, 162 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 163 FN_SEL_CAN0_4, FN_SEL_CAN0_5, 164 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, 165 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, 166 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 167 FN_SEL_ADG_0, FN_SEL_ADG_1, 168 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4, 169 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 170 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, 171 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 172 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 173 FN_SEL_SIM_0, FN_SEL_SIM_1, 174 FN_SEL_SSI8_0, FN_SEL_SSI8_1, 175 176 /* MOD_SEL3 */ 177 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, 178 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, 179 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 180 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 181 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 182 FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3, 183 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, 184 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 185 FN_SEL_MMC_0, FN_SEL_MMC_1, 186 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, 187 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, 188 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3, 189 FN_SEL_IIC1_4, 190 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 191 192 /* MOD_SEL4 */ 193 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, 194 FN_SEL_SOF1_4, 195 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 196 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 197 FN_SEL_RAD_0, FN_SEL_RAD_1, 198 FN_SEL_RCN_0, FN_SEL_RCN_1, 199 FN_SEL_RSP_0, FN_SEL_RSP_1, 200 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3, 201 FN_SEL_SCIF2_4, 202 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3, 203 FN_SEL_SOF2_4, 204 FN_SEL_SSI1_0, FN_SEL_SSI1_1, 205 FN_SEL_SSI0_0, FN_SEL_SSI0_1, 206 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 207 PINMUX_FUNCTION_END, 208 209 PINMUX_MARK_BEGIN, 210 211 EX_CS0_N_MARK, RD_N_MARK, 212 213 AUDIO_CLKA_MARK, 214 215 VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA0_VI0_B1_MARK, 216 VI0_DATA0_VI0_B2_MARK, VI0_DATA0_VI0_B4_MARK, VI0_DATA0_VI0_B5_MARK, 217 VI0_DATA0_VI0_B6_MARK, VI0_DATA0_VI0_B7_MARK, 218 219 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, 220 221 /* IPSR0 IPSR10 */ 222 /* IPSR11 */ 223 VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK, 224 VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK, 225 VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK, 226 SDA4_B_MARK, _MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK, 227 VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK, 228 TX4_B_MARK, SCIFA4_TXD_B_MARK, 229 VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK, 230 RX4_B_MARK, SCIFA4_RXD_B_MARK, 231 VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK, 232 VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK, 233 VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK, 234 VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK, 235 VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK, 236 VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK, 237 VI1_DATA7_MARK, AVB_MDC_MARK, 238 ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK, 239 ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK, 240 241 /* IPSR12 */ 242 ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK, 243 ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK, 244 ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK, 245 SCL2_D_MARK, MSIOF1_RXD_E_MARK, 246 ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK, 247 SDA2_D_MARK, MSIOF1_SCK_E_MARK, 248 ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK, 249 CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK, 250 ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK, 251 CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK, 252 ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK, 253 ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK, 254 ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK, 255 ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK, 256 STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK, 257 ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK, 258 STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK, 259 ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK, 260 261 /* IPSR13 */ 262 PINMUX_MARK_END, 263 }; 264 265 static pinmux_enum_t pinmux_data[] = { 266 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ 267 268 /* OTHER IPSR0 - IPSR10 */ 269 /* IPSR11 */ 270 PINMUX_IPSR_DATA(IP11_2_0, VI0_R5), 271 PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6), 272 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1), 273 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2), 274 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3), 275 PINMUX_IPSR_DATA(IP11_5_3, VI0_R6), 276 PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7), 277 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1), 278 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2), 279 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1), 280 PINMUX_IPSR_DATA(IP11_8_6, VI0_R7), 281 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1), 282 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2), 283 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4), 284 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1), 285 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3), 286 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3), 287 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0), 288 PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0), 289 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1), 290 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1), 291 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1), 292 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0), 293 PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1), 294 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1), 295 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1), 296 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1), 297 PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0), 298 PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2), 299 PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1), 300 PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0), 301 PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3), 302 PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1), 303 PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0), 304 PINMUX_IPSR_DATA(IP11_19, AVB_RXD4), 305 PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0), 306 PINMUX_IPSR_DATA(IP11_20, AVB_RXD5), 307 PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0), 308 PINMUX_IPSR_DATA(IP11_21, AVB_RXD6), 309 PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0), 310 PINMUX_IPSR_DATA(IP11_22, AVB_RXD7), 311 PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0), 312 PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER), 313 PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0), 314 PINMUX_IPSR_DATA(IP11_24, AVB_MDIO), 315 PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0), 316 PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV), 317 PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0), 318 PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC), 319 PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0), 320 PINMUX_IPSR_DATA(IP11_27, AVB_MDC), 321 PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO), 322 PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK), 323 PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2), 324 PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV), 325 PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK), 326 PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2), 327 328 /* IPSR12 */ 329 PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER), 330 PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS), 331 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0), 332 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0), 333 PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0), 334 PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT), 335 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0), 336 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0), 337 PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1), 338 PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK), 339 PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2), 340 PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3), 341 PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4), 342 PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK), 343 PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0), 344 PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2), 345 PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3), 346 PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4), 347 PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK), 348 PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1), 349 PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1), 350 PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2), 351 PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4), 352 PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1), 353 PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2), 354 PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1), 355 PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2), 356 PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4), 357 PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN), 358 PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3), 359 PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0), 360 PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1), 361 PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC), 362 PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4), 363 PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2), 364 PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0), 365 PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5), 366 PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2), 367 PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC), 368 PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6), 369 PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2), 370 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0), 371 PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7), 372 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3), 373 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1), 374 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2), 375 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0), 376 PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN), 377 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3), 378 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1), 379 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2), 380 381 /* IPSR13 - IPSR16 */ 382 }; 383 384 static struct pinmux_gpio pinmux_gpios[] = { 385 PINMUX_GPIO_GP_ALL(), 386 387 /* OTHER, IPSR0 - IPSR10 */ 388 /* IPSR11 */ 389 GPIO_FN(VI0_R5), GPIO_FN(VI2_DATA6), GPIO_FN(GLO_SDATA_B), 390 GPIO_FN(RX0_C), GPIO_FN(SDA1_D), 391 GPIO_FN(VI0_R6), GPIO_FN(VI2_DATA7), 392 GPIO_FN(GLO_SS_B), GPIO_FN(TX1_C), GPIO_FN(SCL4_B), 393 GPIO_FN(VI0_R7), GPIO_FN(GLO_RFON_B), 394 GPIO_FN(RX1_C), GPIO_FN(CAN0_RX_E), 395 GPIO_FN(SDA4_B), GPIO_FN(HRX1_D), GPIO_FN(SCIFB0_RXD_D), 396 GPIO_FN(VI1_HSYNC_N), GPIO_FN(AVB_RXD0), GPIO_FN(TS_SDATA0_B), 397 GPIO_FN(TX4_B), GPIO_FN(SCIFA4_TXD_B), 398 GPIO_FN(VI1_VSYNC_N), GPIO_FN(AVB_RXD1), GPIO_FN(TS_SCK0_B), 399 GPIO_FN(RX4_B), GPIO_FN(SCIFA4_RXD_B), 400 GPIO_FN(VI1_CLKENB), GPIO_FN(AVB_RXD2), GPIO_FN(TS_SDEN0_B), 401 GPIO_FN(VI1_FIELD), GPIO_FN(AVB_RXD3), GPIO_FN(TS_SPSYNC0_B), 402 GPIO_FN(VI1_CLK), GPIO_FN(AVB_RXD4), 403 GPIO_FN(VI1_DATA0), GPIO_FN(AVB_RXD5), 404 GPIO_FN(VI1_DATA1), GPIO_FN(AVB_RXD6), 405 GPIO_FN(VI1_DATA2), GPIO_FN(AVB_RXD7), 406 GPIO_FN(VI1_DATA3), GPIO_FN(AVB_RX_ER), 407 GPIO_FN(VI1_DATA4), GPIO_FN(AVB_MDIO), 408 GPIO_FN(VI1_DATA5), GPIO_FN(AVB_RX_DV), 409 GPIO_FN(VI1_DATA6), GPIO_FN(AVB_MAGIC), 410 GPIO_FN(VI1_DATA7), GPIO_FN(AVB_MDC), 411 GPIO_FN(ETH_MDIO), GPIO_FN(AVB_RX_CLK), GPIO_FN(SCL2_C), 412 GPIO_FN(ETH_CRS_DV), GPIO_FN(AVB_LINK), GPIO_FN(SDA2_C), 413 414 /* IPSR12 */ 415 GPIO_FN(ETH_RX_ER), GPIO_FN(AVB_CRS), GPIO_FN(SCL3), GPIO_FN(SCL7), 416 GPIO_FN(ETH_RXD0), GPIO_FN(AVB_PHY_INT), GPIO_FN(SDA3), GPIO_FN(SDA7), 417 GPIO_FN(ETH_RXD1), GPIO_FN(AVB_GTXREFCLK), GPIO_FN(CAN0_TX_C), 418 GPIO_FN(SCL2_D), GPIO_FN(MSIOF1_RXD_E), 419 GPIO_FN(ETH_LINK), GPIO_FN(AVB_TXD0), GPIO_FN(CAN0_RX_C), 420 GPIO_FN(SDA2_D), GPIO_FN(MSIOF1_SCK_E), 421 GPIO_FN(ETH_REFCLK), GPIO_FN(AVB_TXD1), GPIO_FN(SCIFA3_RXD_B), 422 GPIO_FN(CAN1_RX_C), GPIO_FN(MSIOF1_SYNC_E), 423 GPIO_FN(ETH_TXD1), GPIO_FN(AVB_TXD2), GPIO_FN(SCIFA3_TXD_B), 424 GPIO_FN(CAN1_TX_C), GPIO_FN(MSIOF1_TXD_E), 425 GPIO_FN(ETH_TX_EN), GPIO_FN(AVB_TXD3), 426 GPIO_FN(TCLK1_B), GPIO_FN(CAN_CLK_B), 427 GPIO_FN(ETH_MAGIC), GPIO_FN(AVB_TXD4), GPIO_FN(IETX_C), 428 GPIO_FN(ETH_TXD0), GPIO_FN(AVB_TXD5), GPIO_FN(IECLK_C), 429 GPIO_FN(ETH_MDC), GPIO_FN(AVB_TXD6), GPIO_FN(IERX_C), 430 GPIO_FN(STP_IVCXO27_0), GPIO_FN(AVB_TXD7), GPIO_FN(SCIFB2_TXD_D), 431 GPIO_FN(ADIDATA_B), GPIO_FN(MSIOF0_SYNC_C), 432 GPIO_FN(STP_ISCLK_0), GPIO_FN(AVB_TX_EN), GPIO_FN(SCIFB2_RXD_D), 433 GPIO_FN(ADICS_SAMP_B), GPIO_FN(MSIOF0_SCK_C), 434 435 /* IPSR13 - IPSR16 */ 436 }; 437 438 static struct pinmux_cfg_reg pinmux_config_regs[] = { 439 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { 440 GP_0_31_FN, FN_IP1_22_20, 441 GP_0_30_FN, FN_IP1_19_17, 442 GP_0_29_FN, FN_IP1_16_14, 443 GP_0_28_FN, FN_IP1_13_11, 444 GP_0_27_FN, FN_IP1_10_8, 445 GP_0_26_FN, FN_IP1_7_6, 446 GP_0_25_FN, FN_IP1_5_4, 447 GP_0_24_FN, FN_IP1_3_2, 448 GP_0_23_FN, FN_IP1_1_0, 449 GP_0_22_FN, FN_IP0_30_29, 450 GP_0_21_FN, FN_IP0_28_27, 451 GP_0_20_FN, FN_IP0_26_25, 452 GP_0_19_FN, FN_IP0_24_23, 453 GP_0_18_FN, FN_IP0_22_21, 454 GP_0_17_FN, FN_IP0_20_19, 455 GP_0_16_FN, FN_IP0_18_16, 456 GP_0_15_FN, FN_IP0_15, 457 GP_0_14_FN, FN_IP0_14, 458 GP_0_13_FN, FN_IP0_13, 459 GP_0_12_FN, FN_IP0_12, 460 GP_0_11_FN, FN_IP0_11, 461 GP_0_10_FN, FN_IP0_10, 462 GP_0_9_FN, FN_IP0_9, 463 GP_0_8_FN, FN_IP0_8, 464 GP_0_7_FN, FN_IP0_7, 465 GP_0_6_FN, FN_IP0_6, 466 GP_0_5_FN, FN_IP0_5, 467 GP_0_4_FN, FN_IP0_4, 468 GP_0_3_FN, FN_IP0_3, 469 GP_0_2_FN, FN_IP0_2, 470 GP_0_1_FN, FN_IP0_1, 471 GP_0_0_FN, FN_IP0_0, } 472 }, 473 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { 474 0, 0, 475 0, 0, 476 0, 0, 477 0, 0, 478 0, 0, 479 0, 0, 480 GP_1_25_FN, FN_IP3_21_20, 481 GP_1_24_FN, FN_IP3_19_18, 482 GP_1_23_FN, FN_IP3_17_16, 483 GP_1_22_FN, FN_IP3_15_14, 484 GP_1_21_FN, FN_IP3_13_12, 485 GP_1_20_FN, FN_IP3_11_9, 486 GP_1_19_FN, FN_RD_N, 487 GP_1_18_FN, FN_IP3_8_6, 488 GP_1_17_FN, FN_IP3_5_3, 489 GP_1_16_FN, FN_IP3_2_0, 490 GP_1_15_FN, FN_IP2_29_27, 491 GP_1_14_FN, FN_IP2_26_25, 492 GP_1_13_FN, FN_IP2_24_23, 493 GP_1_12_FN, FN_EX_CS0_N, 494 GP_1_11_FN, FN_IP2_22_21, 495 GP_1_10_FN, FN_IP2_20_19, 496 GP_1_9_FN, FN_IP2_18_16, 497 GP_1_8_FN, FN_IP2_15_13, 498 GP_1_7_FN, FN_IP2_12_10, 499 GP_1_6_FN, FN_IP2_9_7, 500 GP_1_5_FN, FN_IP2_6_5, 501 GP_1_4_FN, FN_IP2_4_3, 502 GP_1_3_FN, FN_IP2_2_0, 503 GP_1_2_FN, FN_IP1_31_29, 504 GP_1_1_FN, FN_IP1_28_26, 505 GP_1_0_FN, FN_IP1_25_23, } 506 }, 507 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { 508 GP_2_31_FN, FN_IP6_7_6, 509 GP_2_30_FN, FN_IP6_5_3, 510 GP_2_29_FN, FN_IP6_2_0, 511 GP_2_28_FN, FN_AUDIO_CLKA, 512 GP_2_27_FN, FN_IP5_31_29, 513 GP_2_26_FN, FN_IP5_28_26, 514 GP_2_25_FN, FN_IP5_25_24, 515 GP_2_24_FN, FN_IP5_23_22, 516 GP_2_23_FN, FN_IP5_21_20, 517 GP_2_22_FN, FN_IP5_19_17, 518 GP_2_21_FN, FN_IP5_16_15, 519 GP_2_20_FN, FN_IP5_14_12, 520 GP_2_19_FN, FN_IP5_11_9, 521 GP_2_18_FN, FN_IP5_8_6, 522 GP_2_17_FN, FN_IP5_5_3, 523 GP_2_16_FN, FN_IP5_2_0, 524 GP_2_15_FN, FN_IP4_30_28, 525 GP_2_14_FN, FN_IP4_27_26, 526 GP_2_13_FN, FN_IP4_25_24, 527 GP_2_12_FN, FN_IP4_23_22, 528 GP_2_11_FN, FN_IP4_21, 529 GP_2_10_FN, FN_IP4_20, 530 GP_2_9_FN, FN_IP4_19, 531 GP_2_8_FN, FN_IP4_18_16, 532 GP_2_7_FN, FN_IP4_15_13, 533 GP_2_6_FN, FN_IP4_12_10, 534 GP_2_5_FN, FN_IP4_9_8, 535 GP_2_4_FN, FN_IP4_7_5, 536 GP_2_3_FN, FN_IP4_4_2, 537 GP_2_2_FN, FN_IP4_1_0, 538 GP_2_1_FN, FN_IP3_30_28, 539 GP_2_0_FN, FN_IP3_27_25 } 540 }, 541 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { 542 GP_3_31_FN, FN_IP9_18_17, 543 GP_3_30_FN, FN_IP9_16, 544 GP_3_29_FN, FN_IP9_15_13, 545 GP_3_28_FN, FN_IP9_12, 546 GP_3_27_FN, FN_IP9_11, 547 GP_3_26_FN, FN_IP9_10_8, 548 GP_3_25_FN, FN_IP9_7, 549 GP_3_24_FN, FN_IP9_6, 550 GP_3_23_FN, FN_IP9_5_3, 551 GP_3_22_FN, FN_IP9_2_0, 552 GP_3_21_FN, FN_IP8_30_28, 553 GP_3_20_FN, FN_IP8_27_26, 554 GP_3_19_FN, FN_IP8_25_24, 555 GP_3_18_FN, FN_IP8_23_21, 556 GP_3_17_FN, FN_IP8_20_18, 557 GP_3_16_FN, FN_IP8_17_15, 558 GP_3_15_FN, FN_IP8_14_12, 559 GP_3_14_FN, FN_IP8_11_9, 560 GP_3_13_FN, FN_IP8_8_6, 561 GP_3_12_FN, FN_IP8_5_3, 562 GP_3_11_FN, FN_IP8_2_0, 563 GP_3_10_FN, FN_IP7_29_27, 564 GP_3_9_FN, FN_IP7_26_24, 565 GP_3_8_FN, FN_IP7_23_21, 566 GP_3_7_FN, FN_IP7_20_19, 567 GP_3_6_FN, FN_IP7_18_17, 568 GP_3_5_FN, FN_IP7_16_15, 569 GP_3_4_FN, FN_IP7_14_13, 570 GP_3_3_FN, FN_IP7_12_11, 571 GP_3_2_FN, FN_IP7_10_9, 572 GP_3_1_FN, FN_IP7_8_6, 573 GP_3_0_FN, FN_IP7_5_3 } 574 }, 575 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { 576 GP_4_31_FN, FN_IP15_5_4, 577 GP_4_30_FN, FN_IP15_3_2, 578 GP_4_29_FN, FN_IP15_1_0, 579 GP_4_28_FN, FN_IP11_8_6, 580 GP_4_27_FN, FN_IP11_5_3, 581 GP_4_26_FN, FN_IP11_2_0, 582 GP_4_25_FN, FN_IP10_31_29, 583 GP_4_24_FN, FN_IP10_28_27, 584 GP_4_23_FN, FN_IP10_26_25, 585 GP_4_22_FN, FN_IP10_24_22, 586 GP_4_21_FN, FN_IP10_21_19, 587 GP_4_20_FN, FN_IP10_18_17, 588 GP_4_19_FN, FN_IP10_16_15, 589 GP_4_18_FN, FN_IP10_14_12, 590 GP_4_17_FN, FN_IP10_11_9, 591 GP_4_16_FN, FN_IP10_8_6, 592 GP_4_15_FN, FN_IP10_5_3, 593 GP_4_14_FN, FN_IP10_2_0, 594 GP_4_13_FN, FN_IP9_31_29, 595 GP_4_12_FN, FN_VI0_DATA0_VI0_B7, 596 GP_4_11_FN, FN_VI0_DATA0_VI0_B6, 597 GP_4_10_FN, FN_VI0_DATA0_VI0_B5, 598 GP_4_9_FN, FN_VI0_DATA0_VI0_B4, 599 GP_4_8_FN, FN_IP9_28_27, 600 GP_4_7_FN, FN_VI0_DATA0_VI0_B2, 601 GP_4_6_FN, FN_VI0_DATA0_VI0_B1, 602 GP_4_5_FN, FN_VI0_DATA0_VI0_B0, 603 GP_4_4_FN, FN_IP9_26_25, 604 GP_4_3_FN, FN_IP9_24_23, 605 GP_4_2_FN, FN_IP9_22_21, 606 GP_4_1_FN, FN_IP9_20_19, 607 GP_4_0_FN, FN_VI0_CLK } 608 }, 609 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { 610 GP_5_31_FN, FN_IP3_24_22, 611 GP_5_30_FN, FN_IP13_9_7, 612 GP_5_29_FN, FN_IP13_6_5, 613 GP_5_28_FN, FN_IP13_4_3, 614 GP_5_27_FN, FN_IP13_2_0, 615 GP_5_26_FN, FN_IP12_29_27, 616 GP_5_25_FN, FN_IP12_26_24, 617 GP_5_24_FN, FN_IP12_23_22, 618 GP_5_23_FN, FN_IP12_21_20, 619 GP_5_22_FN, FN_IP12_19_18, 620 GP_5_21_FN, FN_IP12_17_16, 621 GP_5_20_FN, FN_IP12_15_13, 622 GP_5_19_FN, FN_IP12_12_10, 623 GP_5_18_FN, FN_IP12_9_7, 624 GP_5_17_FN, FN_IP12_6_4, 625 GP_5_16_FN, FN_IP12_3_2, 626 GP_5_15_FN, FN_IP12_1_0, 627 GP_5_14_FN, FN_IP11_31_30, 628 GP_5_13_FN, FN_IP11_29_28, 629 GP_5_12_FN, FN_IP11_27, 630 GP_5_11_FN, FN_IP11_26, 631 GP_5_10_FN, FN_IP11_25, 632 GP_5_9_FN, FN_IP11_24, 633 GP_5_8_FN, FN_IP11_23, 634 GP_5_7_FN, FN_IP11_22, 635 GP_5_6_FN, FN_IP11_21, 636 GP_5_5_FN, FN_IP11_20, 637 GP_5_4_FN, FN_IP11_19, 638 GP_5_3_FN, FN_IP11_18_17, 639 GP_5_2_FN, FN_IP11_16_15, 640 GP_5_1_FN, FN_IP11_14_12, 641 GP_5_0_FN, FN_IP11_11_9 } 642 }, 643 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { 644 0, 0, 645 0, 0, 646 GP_6_29_FN, FN_IP14_31_29, 647 GP_6_28_FN, FN_IP14_28_26, 648 GP_6_27_FN, FN_IP14_25_23, 649 GP_6_26_FN, FN_IP14_22_20, 650 GP_6_25_FN, FN_IP14_19_17, 651 GP_6_24_FN, FN_IP14_16_14, 652 GP_6_23_FN, FN_IP14_13_11, 653 GP_6_22_FN, FN_IP14_10_8, 654 GP_6_21_FN, FN_IP14_7, 655 GP_6_20_FN, FN_IP14_6, 656 GP_6_19_FN, FN_IP14_5, 657 GP_6_18_FN, FN_IP14_4, 658 GP_6_17_FN, FN_IP14_3, 659 GP_6_16_FN, FN_IP14_2, 660 GP_6_15_FN, FN_IP14_1_0, 661 GP_6_14_FN, FN_IP13_30_28, 662 GP_6_13_FN, FN_IP13_27, 663 GP_6_12_FN, FN_IP13_26, 664 GP_6_11_FN, FN_IP13_25, 665 GP_6_10_FN, FN_IP13_24_23, 666 GP_6_9_FN, FN_IP13_22, 667 0, 0, 668 GP_6_7_FN, FN_IP13_21_19, 669 GP_6_6_FN, FN_IP13_18_16, 670 GP_6_5_FN, FN_IP13_15, 671 GP_6_4_FN, FN_IP13_14, 672 GP_6_3_FN, FN_IP13_13, 673 GP_6_2_FN, FN_IP13_12, 674 GP_6_1_FN, FN_IP13_11, 675 GP_6_0_FN, FN_IP13_10 } 676 }, 677 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) { 678 0, 0, 679 0, 0, 680 0, 0, 681 0, 0, 682 0, 0, 683 0, 0, 684 GP_7_25_FN, FN_USB1_PWEN, 685 GP_7_24_FN, FN_USB0_OVC, 686 GP_7_23_FN, FN_USB0_PWEN, 687 GP_7_22_FN, FN_IP15_14_12, 688 GP_7_21_FN, FN_IP15_11_9, 689 GP_7_20_FN, FN_IP15_8_6, 690 GP_7_19_FN, FN_IP7_2_0, 691 GP_7_18_FN, FN_IP6_29_27, 692 GP_7_17_FN, FN_IP6_26_24, 693 GP_7_16_FN, FN_IP6_23_21, 694 GP_7_15_FN, FN_IP6_20_19, 695 GP_7_14_FN, FN_IP6_18_16, 696 GP_7_13_FN, FN_IP6_15_14, 697 GP_7_12_FN, FN_IP6_13_12, 698 GP_7_11_FN, FN_IP6_11_10, 699 GP_7_10_FN, FN_IP6_9_8, 700 GP_7_9_FN, FN_IP16_11_10, 701 GP_7_8_FN, FN_IP16_9_8, 702 GP_7_7_FN, FN_IP16_7_6, 703 GP_7_6_FN, FN_IP16_5_3, 704 GP_7_5_FN, FN_IP16_2_0, 705 GP_7_4_FN, FN_IP15_29_27, 706 GP_7_3_FN, FN_IP15_26_24, 707 GP_7_2_FN, FN_IP15_23_21, 708 GP_7_1_FN, FN_IP15_20_18, 709 GP_7_0_FN, FN_IP15_17_15 } 710 }, 711 /* IPSR0 - IPSR10 */ 712 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, 713 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 714 3, 3, 3, 3, 3) { 715 /* IP11_31_30 [2] */ 716 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0, 717 /* IP11_29_28 [2] */ 718 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0, 719 /* IP11_27 [1] */ 720 FN_VI1_DATA7, FN_AVB_MDC, 721 /* IP11_26 [1] */ 722 FN_VI1_DATA6, FN_AVB_MAGIC, 723 /* IP11_25 [1] */ 724 FN_VI1_DATA5, FN_AVB_RX_DV, 725 /* IP11_24 [1] */ 726 FN_VI1_DATA4, FN_AVB_MDIO, 727 /* IP11_23 [1] */ 728 FN_VI1_DATA3, FN_AVB_RX_ER, 729 /* IP11_22 [1] */ 730 FN_VI1_DATA2, FN_AVB_RXD7, 731 /* IP11_21 [1] */ 732 FN_VI1_DATA1, FN_AVB_RXD6, 733 /* IP11_20 [1] */ 734 FN_VI1_DATA0, FN_AVB_RXD5, 735 /* IP11_19 [1] */ 736 FN_VI1_CLK, FN_AVB_RXD4, 737 /* IP11_18_17 [2] */ 738 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0, 739 /* IP11_16_15 [2] */ 740 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0, 741 /* IP11_14_12 [3] */ 742 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, 743 FN_RX4_B, FN_SCIFA4_RXD_B, 744 0, 0, 0, 745 /* IP11_11_9 [3] */ 746 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, 747 FN_TX4_B, FN_SCIFA4_TXD_B, 748 0, 0, 0, 749 /* IP11_8_6 [3] */ 750 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, 751 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0, 752 /* IP11_5_3 [3] */ 753 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B, 754 0, 0, 0, 755 /* IP11_2_0 [3] */ 756 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D, 757 0, 0, 0, } 758 }, 759 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, 760 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) { 761 /* IP12_31_30 [2] */ 762 0, 0, 0, 0, 763 /* IP12_29_27 [3] */ 764 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, 765 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, 766 0, 0, 0, 767 /* IP12_26_24 [3] */ 768 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, 769 FN_ADIDATA_B, FN_MSIOF0_SYNC_C, 770 0, 0, 0, 771 /* IP12_23_22 [2] */ 772 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0, 773 /* IP12_21_20 [2] */ 774 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0, 775 /* IP12_19_18 [2] */ 776 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0, 777 /* IP12_17_16 [2] */ 778 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, 779 /* IP12_15_13 [3] */ 780 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, 781 FN_CAN1_TX_C, FN_MSIOF1_TXD_E, 782 0, 0, 0, 783 /* IP12_12_10 [3] */ 784 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, 785 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, 786 0, 0, 0, 787 /* IP12_9_7 [3] */ 788 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, 789 FN_SDA2_D, FN_MSIOF1_SCK_E, 790 0, 0, 0, 791 /* IP12_6_4 [3] */ 792 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, 793 FN_SCL2_D, FN_MSIOF1_RXD_E, 794 0, 0, 0, 795 /* IP12_3_2 [2] */ 796 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7, 797 /* IP12_1_0 [2] */ 798 FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, } 799 }, 800 801 /* IPSR13 - IPSR16 */ 802 803 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, 804 1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 805 3, 2, 2, 2, 1, 2, 2, 2) { 806 /* RESEVED [1] */ 807 0, 0, 808 /* SEL_SCIF1 [2] */ 809 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 810 /* SEL_SCIFB [2] */ 811 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, 812 /* SEL_SCIFB2 [2] */ 813 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, 814 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, 815 /* SEL_SCIFB1 [3] */ 816 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, 817 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, 818 0, 0, 0, 0, 819 /* SEL_SCIFA1 [2] */ 820 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0, 821 /* SEL_SSI9 [1] */ 822 FN_SEL_SSI9_0, FN_SEL_SSI9_1, 823 /* SEL_SCFA [1] */ 824 FN_SEL_SCFA_0, FN_SEL_SCFA_1, 825 /* SEL_QSP [1] */ 826 FN_SEL_QSP_0, FN_SEL_QSP_1, 827 /* SEL_SSI7 [1] */ 828 FN_SEL_SSI7_0, FN_SEL_SSI7_1, 829 /* SEL_HSCIF1 [3] */ 830 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 831 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4, 832 0, 0, 0, 833 /* RESEVED [2] */ 834 0, 0, 0, 0, 835 /* SEL_VI1 [2] */ 836 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0, 837 /* RESEVED [2] */ 838 0, 0, 0, 0, 839 /* SEL_TMU [1] */ 840 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 841 /* SEL_LBS [2] */ 842 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, 843 /* SEL_TSIF0 [2] */ 844 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 845 /* SEL_SOF0 [2] */ 846 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, } 847 }, 848 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, 849 3, 1, 1, 3, 2, 1, 1, 2, 2, 850 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) { 851 /* SEL_SCIF0 [3] */ 852 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, 853 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4, 854 0, 0, 0, 855 /* RESEVED [1] */ 856 0, 0, 857 /* SEL_SCIF [1] */ 858 FN_SEL_SCIF_0, FN_SEL_SCIF_1, 859 /* SEL_CAN0 [3] */ 860 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 861 FN_SEL_CAN0_4, FN_SEL_CAN0_5, 862 0, 0, 863 /* SEL_CAN1 [2] */ 864 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, 865 /* RESEVED [1] */ 866 0, 0, 867 /* SEL_SCIFA2 [1] */ 868 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, 869 /* SEL_SCIF4 [2] */ 870 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0, 871 /* RESEVED [2] */ 872 0, 0, 0, 0, 873 /* SEL_ADG [1] */ 874 FN_SEL_ADG_0, FN_SEL_ADG_1, 875 /* SEL_FM [3] */ 876 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, 877 FN_SEL_FM_3, FN_SEL_FM_4, 878 0, 0, 0, 879 /* SEL_SCIFA5 [2] */ 880 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0, 881 /* RESEVED [1] */ 882 0, 0, 883 /* SEL_GPS [2] */ 884 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, 885 /* SEL_SCIFA4 [2] */ 886 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0, 887 /* SEL_SCIFA3 [2] */ 888 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0, 889 /* SEL_SIM [1] */ 890 FN_SEL_SIM_0, FN_SEL_SIM_1, 891 /* RESEVED [1] */ 892 0, 0, 893 /* SEL_SSI8 [1] */ 894 FN_SEL_SSI8_0, FN_SEL_SSI8_1, } 895 }, 896 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, 897 2, 2, 2, 2, 2, 2, 2, 2, 898 1, 1, 2, 2, 3, 2, 2, 2, 1) { 899 /* SEL_HSCIF2 [2] */ 900 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, 901 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, 902 /* SEL_CANCLK [2] */ 903 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, 904 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, 905 /* SEL_IIC8 [2] */ 906 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0, 907 /* SEL_IIC7 [2] */ 908 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0, 909 /* SEL_IIC4 [2] */ 910 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0, 911 /* SEL_IIC3 [2] */ 912 FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3, 913 /* SEL_SCIF3 [2] */ 914 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, 915 /* SEL_IEB [2] */ 916 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, 917 /* SEL_MMC [1] */ 918 FN_SEL_MMC_0, FN_SEL_MMC_1, 919 /* SEL_SCIF5 [1] */ 920 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, 921 /* RESEVED [2] */ 922 0, 0, 0, 0, 923 /* SEL_IIC2 [2] */ 924 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, 925 /* SEL_IIC1 [3] */ 926 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3, 927 FN_SEL_IIC1_4, 928 0, 0, 0, 929 /* SEL_IIC0 [2] */ 930 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0, 931 /* RESEVED [2] */ 932 0, 0, 0, 0, 933 /* RESEVED [2] */ 934 0, 0, 0, 0, 935 /* RESEVED [1] */ 936 0, 0, } 937 }, 938 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32, 939 3, 2, 2, 1, 1, 1, 1, 3, 2, 940 2, 3, 1, 1, 1, 2, 2, 2, 2) { 941 /* SEL_SOF1 [3] */ 942 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, 943 FN_SEL_SOF1_4, 944 0, 0, 0, 945 /* SEL_HSCIF0 [2] */ 946 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0, 947 /* SEL_DIS [2] */ 948 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0, 949 /* RESEVED [1] */ 950 0, 0, 951 /* SEL_RAD [1] */ 952 FN_SEL_RAD_0, FN_SEL_RAD_1, 953 /* SEL_RCN [1] */ 954 FN_SEL_RCN_0, FN_SEL_RCN_1, 955 /* SEL_RSP [1] */ 956 FN_SEL_RSP_0, FN_SEL_RSP_1, 957 /* SEL_SCIF2 [3] */ 958 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 959 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4, 960 0, 0, 0, 961 /* RESEVED [2] */ 962 0, 0, 0, 0, 963 /* RESEVED [2] */ 964 0, 0, 0, 0, 965 /* SEL_SOF2 [3] */ 966 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, 967 FN_SEL_SOF2_3, FN_SEL_SOF2_4, 968 0, 0, 0, 969 /* RESEVED [1] */ 970 0, 0, 971 /* SEL_SSI1 [1] */ 972 FN_SEL_SSI1_0, FN_SEL_SSI1_1, 973 /* SEL_SSI0 [1] */ 974 FN_SEL_SSI0_0, FN_SEL_SSI0_1, 975 /* SEL_SSP [2] */ 976 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0, 977 /* RESEVED [2] */ 978 0, 0, 0, 0, 979 /* RESEVED [2] */ 980 0, 0, 0, 0, 981 /* RESEVED [2] */ 982 0, 0, 0, 0, } 983 }, 984 { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } }, 985 { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { 986 0, 0, 987 0, 0, 988 0, 0, 989 0, 0, 990 0, 0, 991 0, 0, 992 GP_1_25_IN, GP_1_25_OUT, 993 GP_1_24_IN, GP_1_24_OUT, 994 GP_1_23_IN, GP_1_23_OUT, 995 GP_1_22_IN, GP_1_22_OUT, 996 GP_1_21_IN, GP_1_21_OUT, 997 GP_1_20_IN, GP_1_20_OUT, 998 GP_1_19_IN, GP_1_19_OUT, 999 GP_1_18_IN, GP_1_18_OUT, 1000 GP_1_17_IN, GP_1_17_OUT, 1001 GP_1_16_IN, GP_1_16_OUT, 1002 GP_1_15_IN, GP_1_15_OUT, 1003 GP_1_14_IN, GP_1_14_OUT, 1004 GP_1_13_IN, GP_1_13_OUT, 1005 GP_1_12_IN, GP_1_12_OUT, 1006 GP_1_11_IN, GP_1_11_OUT, 1007 GP_1_10_IN, GP_1_10_OUT, 1008 GP_1_9_IN, GP_1_9_OUT, 1009 GP_1_8_IN, GP_1_8_OUT, 1010 GP_1_7_IN, GP_1_7_OUT, 1011 GP_1_6_IN, GP_1_6_OUT, 1012 GP_1_5_IN, GP_1_5_OUT, 1013 GP_1_4_IN, GP_1_4_OUT, 1014 GP_1_3_IN, GP_1_3_OUT, 1015 GP_1_2_IN, GP_1_2_OUT, 1016 GP_1_1_IN, GP_1_1_OUT, 1017 GP_1_0_IN, GP_1_0_OUT, } 1018 }, 1019 { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } }, 1020 { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } }, 1021 { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } }, 1022 { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } }, 1023 { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { GP_INOUTSEL(6) } }, 1024 { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) { 1025 0, 0, 1026 0, 0, 1027 0, 0, 1028 0, 0, 1029 0, 0, 1030 0, 0, 1031 GP_7_25_IN, GP_7_25_OUT, 1032 GP_7_24_IN, GP_7_24_OUT, 1033 GP_7_23_IN, GP_7_23_OUT, 1034 GP_7_22_IN, GP_7_22_OUT, 1035 GP_7_21_IN, GP_7_21_OUT, 1036 GP_7_20_IN, GP_7_20_OUT, 1037 GP_7_19_IN, GP_7_19_OUT, 1038 GP_7_18_IN, GP_7_18_OUT, 1039 GP_7_17_IN, GP_7_17_OUT, 1040 GP_7_16_IN, GP_7_16_OUT, 1041 GP_7_15_IN, GP_7_15_OUT, 1042 GP_7_14_IN, GP_7_14_OUT, 1043 GP_7_13_IN, GP_7_13_OUT, 1044 GP_7_12_IN, GP_7_12_OUT, 1045 GP_7_11_IN, GP_7_11_OUT, 1046 GP_7_10_IN, GP_7_10_OUT, 1047 GP_7_9_IN, GP_7_9_OUT, 1048 GP_7_8_IN, GP_7_8_OUT, 1049 GP_7_7_IN, GP_7_7_OUT, 1050 GP_7_6_IN, GP_7_6_OUT, 1051 GP_7_5_IN, GP_7_5_OUT, 1052 GP_7_4_IN, GP_7_4_OUT, 1053 GP_7_3_IN, GP_7_3_OUT, 1054 GP_7_2_IN, GP_7_2_OUT, 1055 GP_7_1_IN, GP_7_1_OUT, 1056 GP_7_0_IN, GP_7_0_OUT, } 1057 }, 1058 { }, 1059 }; 1060 1061 static struct pinmux_data_reg pinmux_data_regs[] = { 1062 { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } }, 1063 { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { 1064 0, 0, 0, 0, 1065 0, 0, GP_1_25_DATA, GP_1_24_DATA, 1066 GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, 1067 GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, 1068 GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, 1069 GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, 1070 GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, 1071 GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } 1072 }, 1073 { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } }, 1074 { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } }, 1075 { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } }, 1076 { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } }, 1077 { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { GP_INDT(6) } }, 1078 { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) { 1079 0, 0, 0, 0, 1080 0, 0, GP_7_25_DATA, GP_7_24_DATA, 1081 GP_7_23_DATA, GP_7_22_DATA, GP_7_21_DATA, GP_7_20_DATA, 1082 GP_7_19_DATA, GP_7_18_DATA, GP_7_17_DATA, GP_7_16_DATA, 1083 GP_7_15_DATA, GP_7_14_DATA, GP_7_13_DATA, GP_7_12_DATA, 1084 GP_7_11_DATA, GP_7_10_DATA, GP_7_9_DATA, GP_7_8_DATA, 1085 GP_7_7_DATA, GP_7_6_DATA, GP_7_5_DATA, GP_7_4_DATA, 1086 GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA } 1087 }, 1088 { }, 1089 }; 1090 1091 static struct pinmux_info r8a7791_pinmux_info = { 1092 .name = "r8a7791_pfc", 1093 1094 .unlock_reg = 0xe6060000, /* PMMR */ 1095 1096 .reserved_id = PINMUX_RESERVED, 1097 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, 1098 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 1099 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 1100 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, 1101 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 1102 1103 .first_gpio = GPIO_GP_0_0, 1104 .last_gpio = GPIO_FN_MSIOF0_SCK_C /* GPIO_FN_CAN1_RX_B */, 1105 1106 .gpios = pinmux_gpios, 1107 .cfg_regs = pinmux_config_regs, 1108 .data_regs = pinmux_data_regs, 1109 1110 .gpio_data = pinmux_data, 1111 .gpio_data_size = ARRAY_SIZE(pinmux_data), 1112 }; 1113 1114 void r8a7791_pinmux_init(void) 1115 { 1116 register_pinmux(&r8a7791_pinmux_info); 1117 } 1118