1*2dea3b3eSMarek Vasut /* 2*2dea3b3eSMarek Vasut * arch/arm/include/asm/arch-rcar_gen3/r8a7796.h 3*2dea3b3eSMarek Vasut * This file defines registers and value for r8a7796. 4*2dea3b3eSMarek Vasut * 5*2dea3b3eSMarek Vasut * Copyright (C) 2016 Renesas Electronics Corporation 6*2dea3b3eSMarek Vasut * 7*2dea3b3eSMarek Vasut * SPDX-License-Identifier: GPL-2.0+ 8*2dea3b3eSMarek Vasut */ 9*2dea3b3eSMarek Vasut 10*2dea3b3eSMarek Vasut #ifndef __ASM_ARCH_R8A7796_H 11*2dea3b3eSMarek Vasut #define __ASM_ARCH_R8A7796_H 12*2dea3b3eSMarek Vasut 13*2dea3b3eSMarek Vasut #include "rcar-gen3-base.h" 14*2dea3b3eSMarek Vasut 15*2dea3b3eSMarek Vasut /* Module stop control/status register bits */ 16*2dea3b3eSMarek Vasut #define MSTP0_BITS 0x00200000 17*2dea3b3eSMarek Vasut #define MSTP1_BITS 0xFFFFFFFF 18*2dea3b3eSMarek Vasut #define MSTP2_BITS 0x340E2FDC 19*2dea3b3eSMarek Vasut #define MSTP3_BITS 0xFFFFFFDF 20*2dea3b3eSMarek Vasut #define MSTP4_BITS 0x80000184 21*2dea3b3eSMarek Vasut #define MSTP5_BITS 0xC3FFFFFF 22*2dea3b3eSMarek Vasut #define MSTP6_BITS 0xFFFFFFFF 23*2dea3b3eSMarek Vasut #define MSTP7_BITS 0xFFFFFFFF 24*2dea3b3eSMarek Vasut #define MSTP8_BITS 0x01F1FFF7 25*2dea3b3eSMarek Vasut #define MSTP9_BITS 0xFFFFFFFE 26*2dea3b3eSMarek Vasut #define MSTP10_BITS 0xFFFEFFE0 27*2dea3b3eSMarek Vasut #define MSTP11_BITS 0x000000B7 28*2dea3b3eSMarek Vasut 29*2dea3b3eSMarek Vasut /* SDHI */ 30*2dea3b3eSMarek Vasut #define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 31*2dea3b3eSMarek Vasut #define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 32*2dea3b3eSMarek Vasut #define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */ 33*2dea3b3eSMarek Vasut #define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 /* either MMC1 */ 34*2dea3b3eSMarek Vasut #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4 35*2dea3b3eSMarek Vasut 36*2dea3b3eSMarek Vasut #endif /* __ASM_ARCH_R8A7796_H */ 37