xref: /rk3399_rockchip-uboot/arch/arm/mach-rmobile/include/mach/r8a7792.h (revision c98b171e1098f94b2ff7720c45a25a602882f876)
1*6f107e4cSmasakazu.mochizuki.wd@hitachi.com /*
2*6f107e4cSmasakazu.mochizuki.wd@hitachi.com  * arch/arm/include/asm/arch-rmobile/r8a7792.h
3*6f107e4cSmasakazu.mochizuki.wd@hitachi.com  *
4*6f107e4cSmasakazu.mochizuki.wd@hitachi.com  * Copyright (C) 2016 Renesas Electronics Corporation
5*6f107e4cSmasakazu.mochizuki.wd@hitachi.com  *
6*6f107e4cSmasakazu.mochizuki.wd@hitachi.com  * SPDX-License-Identifier: GPL-2.0
7*6f107e4cSmasakazu.mochizuki.wd@hitachi.com */
8*6f107e4cSmasakazu.mochizuki.wd@hitachi.com 
9*6f107e4cSmasakazu.mochizuki.wd@hitachi.com #ifndef __ASM_ARCH_R8A7792_H
10*6f107e4cSmasakazu.mochizuki.wd@hitachi.com #define __ASM_ARCH_R8A7792_H
11*6f107e4cSmasakazu.mochizuki.wd@hitachi.com 
12*6f107e4cSmasakazu.mochizuki.wd@hitachi.com #include "rcar-base.h"
13*6f107e4cSmasakazu.mochizuki.wd@hitachi.com 
14*6f107e4cSmasakazu.mochizuki.wd@hitachi.com /* SH-I2C */
15*6f107e4cSmasakazu.mochizuki.wd@hitachi.com #define CONFIG_SYS_I2C_SH_BASE2	0xE6520000
16*6f107e4cSmasakazu.mochizuki.wd@hitachi.com #define CONFIG_SYS_I2C_SH_BASE3	0xE60B0000
17*6f107e4cSmasakazu.mochizuki.wd@hitachi.com 
18*6f107e4cSmasakazu.mochizuki.wd@hitachi.com /* Module stop control/status register bits */
19*6f107e4cSmasakazu.mochizuki.wd@hitachi.com #define MSTP0_BITS	0x00400801
20*6f107e4cSmasakazu.mochizuki.wd@hitachi.com #define MSTP1_BITS	0x9B6F987F
21*6f107e4cSmasakazu.mochizuki.wd@hitachi.com #define MSTP2_BITS	0x108CE100
22*6f107e4cSmasakazu.mochizuki.wd@hitachi.com #define MSTP3_BITS	0x20004010
23*6f107e4cSmasakazu.mochizuki.wd@hitachi.com #define MSTP4_BITS	0x80000184
24*6f107e4cSmasakazu.mochizuki.wd@hitachi.com #define MSTP5_BITS	0x44C00004
25*6f107e4cSmasakazu.mochizuki.wd@hitachi.com #define MSTP7_BITS	0x01BF0000
26*6f107e4cSmasakazu.mochizuki.wd@hitachi.com #define MSTP8_BITS	0x1FE01FB0
27*6f107e4cSmasakazu.mochizuki.wd@hitachi.com #define MSTP9_BITS	0xFE2BFFB2
28*6f107e4cSmasakazu.mochizuki.wd@hitachi.com #define MSTP10_BITS	0x00001820
29*6f107e4cSmasakazu.mochizuki.wd@hitachi.com #define MSTP11_BITS	0x00000008
30*6f107e4cSmasakazu.mochizuki.wd@hitachi.com 
31*6f107e4cSmasakazu.mochizuki.wd@hitachi.com /* SDHI */
32*6f107e4cSmasakazu.mochizuki.wd@hitachi.com #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1
33*6f107e4cSmasakazu.mochizuki.wd@hitachi.com 
34*6f107e4cSmasakazu.mochizuki.wd@hitachi.com #endif /* __ASM_ARCH_R8A7792_H */
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