1*fd697ecfSMasahiro Yamada /* 2*fd697ecfSMasahiro Yamada * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 3*fd697ecfSMasahiro Yamada * 4*fd697ecfSMasahiro Yamada * Based on original Kirkwood support which is 5*fd697ecfSMasahiro Yamada * (C) Copyright 2009 6*fd697ecfSMasahiro Yamada * Marvell Semiconductor <www.marvell.com> 7*fd697ecfSMasahiro Yamada * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 8*fd697ecfSMasahiro Yamada * 9*fd697ecfSMasahiro Yamada * Header file for Marvell's Orion SoC with Feroceon CPU core. 10*fd697ecfSMasahiro Yamada * 11*fd697ecfSMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 12*fd697ecfSMasahiro Yamada */ 13*fd697ecfSMasahiro Yamada 14*fd697ecfSMasahiro Yamada #ifndef _ASM_ARCH_ORION5X_H 15*fd697ecfSMasahiro Yamada #define _ASM_ARCH_ORION5X_H 16*fd697ecfSMasahiro Yamada 17*fd697ecfSMasahiro Yamada #if defined(CONFIG_FEROCEON) 18*fd697ecfSMasahiro Yamada 19*fd697ecfSMasahiro Yamada /* SOC specific definations */ 20*fd697ecfSMasahiro Yamada #define ORION5X_REGISTER(x) (ORION5X_REGS_PHY_BASE + x) 21*fd697ecfSMasahiro Yamada 22*fd697ecfSMasahiro Yamada /* Documented registers */ 23*fd697ecfSMasahiro Yamada #define ORION5X_DRAM_BASE (ORION5X_REGISTER(0x01500)) 24*fd697ecfSMasahiro Yamada #define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000)) 25*fd697ecfSMasahiro Yamada #define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000)) 26*fd697ecfSMasahiro Yamada #define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100)) 27*fd697ecfSMasahiro Yamada #define ORION5X_MPP_BASE (ORION5X_REGISTER(0x10000)) 28*fd697ecfSMasahiro Yamada #define ORION5X_GPIO_BASE (ORION5X_REGISTER(0x10100)) 29*fd697ecfSMasahiro Yamada #define ORION5X_CPU_WIN_BASE (ORION5X_REGISTER(0x20000)) 30*fd697ecfSMasahiro Yamada #define ORION5X_CPU_REG_BASE (ORION5X_REGISTER(0x20100)) 31*fd697ecfSMasahiro Yamada #define ORION5X_TIMER_BASE (ORION5X_REGISTER(0x20300)) 32*fd697ecfSMasahiro Yamada #define ORION5X_REG_PCI_BASE (ORION5X_REGISTER(0x30000)) 33*fd697ecfSMasahiro Yamada #define ORION5X_REG_PCIE_BASE (ORION5X_REGISTER(0x40000)) 34*fd697ecfSMasahiro Yamada #define ORION5X_USB20_PORT0_BASE (ORION5X_REGISTER(0x50000)) 35*fd697ecfSMasahiro Yamada #define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000)) 36*fd697ecfSMasahiro Yamada #define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000)) 37*fd697ecfSMasahiro Yamada #define ORION5X_SATA_BASE (ORION5X_REGISTER(0x80000)) 38*fd697ecfSMasahiro Yamada #define ORION5X_SATA_PORT0_OFFSET 0x2000 39*fd697ecfSMasahiro Yamada #define ORION5X_SATA_PORT1_OFFSET 0x4000 40*fd697ecfSMasahiro Yamada 41*fd697ecfSMasahiro Yamada /* Orion5x GbE controller has a single port */ 42*fd697ecfSMasahiro Yamada #define MAX_MVGBE_DEVS 1 43*fd697ecfSMasahiro Yamada #define MVGBE0_BASE ORION5X_EGIGA_BASE 44*fd697ecfSMasahiro Yamada 45*fd697ecfSMasahiro Yamada /* Orion5x USB Host controller is port 1 */ 46*fd697ecfSMasahiro Yamada #define MVUSB0_BASE ORION5X_USB20_HOST_PORT_BASE 47*fd697ecfSMasahiro Yamada #define MVUSB0_CPU_ATTR_DRAM_CS0 ORION5X_ATTR_DRAM_CS0 48*fd697ecfSMasahiro Yamada #define MVUSB0_CPU_ATTR_DRAM_CS1 ORION5X_ATTR_DRAM_CS1 49*fd697ecfSMasahiro Yamada #define MVUSB0_CPU_ATTR_DRAM_CS2 ORION5X_ATTR_DRAM_CS2 50*fd697ecfSMasahiro Yamada #define MVUSB0_CPU_ATTR_DRAM_CS3 ORION5X_ATTR_DRAM_CS3 51*fd697ecfSMasahiro Yamada 52*fd697ecfSMasahiro Yamada /* Kirkwood CPU memory windows */ 53*fd697ecfSMasahiro Yamada #define MVCPU_WIN_CTRL_DATA ORION5X_CPU_WIN_CTRL_DATA 54*fd697ecfSMasahiro Yamada #define MVCPU_WIN_ENABLE ORION5X_WIN_ENABLE 55*fd697ecfSMasahiro Yamada #define MVCPU_WIN_DISABLE ORION5X_WIN_DISABLE 56*fd697ecfSMasahiro Yamada 57*fd697ecfSMasahiro Yamada #define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024) 58*fd697ecfSMasahiro Yamada 59*fd697ecfSMasahiro Yamada /* include here SoC variants. 5181, 5281, 6183 should go here when 60*fd697ecfSMasahiro Yamada adding support for them, and this comment should then be updated. */ 61*fd697ecfSMasahiro Yamada #if defined(CONFIG_88F5182) 62*fd697ecfSMasahiro Yamada #include <asm/arch/mv88f5182.h> 63*fd697ecfSMasahiro Yamada #else 64*fd697ecfSMasahiro Yamada #error "SOC Name not defined" 65*fd697ecfSMasahiro Yamada #endif 66*fd697ecfSMasahiro Yamada #endif /* CONFIG_FEROCEON */ 67*fd697ecfSMasahiro Yamada #endif /* _ASM_ARCH_ORION5X_H */ 68