1*3e93b4e6SMasahiro Yamada /* 2*3e93b4e6SMasahiro Yamada * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 3*3e93b4e6SMasahiro Yamada * 4*3e93b4e6SMasahiro Yamada * Based on original Kirkwood support which is 5*3e93b4e6SMasahiro Yamada * (C) Copyright 2009 6*3e93b4e6SMasahiro Yamada * Marvell Semiconductor <www.marvell.com> 7*3e93b4e6SMasahiro Yamada * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 8*3e93b4e6SMasahiro Yamada * 9*3e93b4e6SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 10*3e93b4e6SMasahiro Yamada */ 11*3e93b4e6SMasahiro Yamada 12*3e93b4e6SMasahiro Yamada #include <common.h> 13*3e93b4e6SMasahiro Yamada #include <config.h> 14*3e93b4e6SMasahiro Yamada #include <asm/arch/cpu.h> 15*3e93b4e6SMasahiro Yamada 16*3e93b4e6SMasahiro Yamada DECLARE_GLOBAL_DATA_PTR; 17*3e93b4e6SMasahiro Yamada 18*3e93b4e6SMasahiro Yamada /* 19*3e93b4e6SMasahiro Yamada * orion5x_sdram_bar - reads SDRAM Base Address Register 20*3e93b4e6SMasahiro Yamada */ 21*3e93b4e6SMasahiro Yamada u32 orion5x_sdram_bar(enum memory_bank bank) 22*3e93b4e6SMasahiro Yamada { 23*3e93b4e6SMasahiro Yamada struct orion5x_ddr_addr_decode_registers *winregs = 24*3e93b4e6SMasahiro Yamada (struct orion5x_ddr_addr_decode_registers *) 25*3e93b4e6SMasahiro Yamada ORION5X_DRAM_BASE; 26*3e93b4e6SMasahiro Yamada 27*3e93b4e6SMasahiro Yamada u32 result = 0; 28*3e93b4e6SMasahiro Yamada u32 enable = 0x01 & winregs[bank].size; 29*3e93b4e6SMasahiro Yamada 30*3e93b4e6SMasahiro Yamada if ((!enable) || (bank > BANK3)) 31*3e93b4e6SMasahiro Yamada return 0; 32*3e93b4e6SMasahiro Yamada 33*3e93b4e6SMasahiro Yamada result = winregs[bank].base; 34*3e93b4e6SMasahiro Yamada return result; 35*3e93b4e6SMasahiro Yamada } 36*3e93b4e6SMasahiro Yamada int dram_init (void) 37*3e93b4e6SMasahiro Yamada { 38*3e93b4e6SMasahiro Yamada /* dram_init must store complete ramsize in gd->ram_size */ 39*3e93b4e6SMasahiro Yamada gd->ram_size = get_ram_size( 40*3e93b4e6SMasahiro Yamada (long *) orion5x_sdram_bar(0), 41*3e93b4e6SMasahiro Yamada CONFIG_MAX_RAM_BANK_SIZE); 42*3e93b4e6SMasahiro Yamada return 0; 43*3e93b4e6SMasahiro Yamada } 44*3e93b4e6SMasahiro Yamada 45*3e93b4e6SMasahiro Yamada void dram_init_banksize (void) 46*3e93b4e6SMasahiro Yamada { 47*3e93b4e6SMasahiro Yamada int i; 48*3e93b4e6SMasahiro Yamada 49*3e93b4e6SMasahiro Yamada for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 50*3e93b4e6SMasahiro Yamada gd->bd->bi_dram[i].start = orion5x_sdram_bar(i); 51*3e93b4e6SMasahiro Yamada gd->bd->bi_dram[i].size = get_ram_size( 52*3e93b4e6SMasahiro Yamada (long *) (gd->bd->bi_dram[i].start), 53*3e93b4e6SMasahiro Yamada CONFIG_MAX_RAM_BANK_SIZE); 54*3e93b4e6SMasahiro Yamada } 55*3e93b4e6SMasahiro Yamada } 56