1350b50eeSStefan Roese /* 2a5f88877SStefan Roese * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de> 3350b50eeSStefan Roese * 4350b50eeSStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5350b50eeSStefan Roese */ 6350b50eeSStefan Roese 7350b50eeSStefan Roese #include <common.h> 86451223aSStefan Roese #include <dm.h> 96451223aSStefan Roese #include <debug_uart.h> 106451223aSStefan Roese #include <fdtdec.h> 11350b50eeSStefan Roese #include <spl.h> 12350b50eeSStefan Roese #include <asm/io.h> 13350b50eeSStefan Roese #include <asm/arch/cpu.h> 14350b50eeSStefan Roese #include <asm/arch/soc.h> 15350b50eeSStefan Roese get_boot_device(void)16a5f88877SStefan Roesestatic u32 get_boot_device(void) 17350b50eeSStefan Roese { 18a5f88877SStefan Roese u32 val; 19a5f88877SStefan Roese u32 boot_device; 20a5f88877SStefan Roese 21f4db6c97SStefan Roese /* 22f4db6c97SStefan Roese * First check, if UART boot-mode is active. This can only 23f4db6c97SStefan Roese * be done, via the bootrom error register. Here the 24f4db6c97SStefan Roese * MSB marks if the UART mode is active. 25f4db6c97SStefan Roese */ 26f4db6c97SStefan Roese val = readl(CONFIG_BOOTROM_ERR_REG); 27f4db6c97SStefan Roese boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS; 28f4db6c97SStefan Roese debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device); 29f4db6c97SStefan Roese if (boot_device == BOOTROM_ERR_MODE_UART) 30f4db6c97SStefan Roese return BOOT_DEVICE_UART; 31f4db6c97SStefan Roese 32f4db6c97SStefan Roese /* 33f4db6c97SStefan Roese * Now check the SAR register for the strapped boot-device 34f4db6c97SStefan Roese */ 35a5f88877SStefan Roese val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ 36a5f88877SStefan Roese boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS; 37f4db6c97SStefan Roese debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device); 38a5f88877SStefan Roese switch (boot_device) { 39a5f88877SStefan Roese #ifdef CONFIG_SPL_MMC_SUPPORT 40a5f88877SStefan Roese case BOOT_FROM_MMC: 41a5f88877SStefan Roese case BOOT_FROM_MMC_ALT: 428ed43b96SStefan Roese return BOOT_DEVICE_MMC1; 438ed43b96SStefan Roese #endif 44a5f88877SStefan Roese case BOOT_FROM_UART: 45a5f88877SStefan Roese return BOOT_DEVICE_UART; 46a5f88877SStefan Roese case BOOT_FROM_SPI: 47a5f88877SStefan Roese default: 48a5f88877SStefan Roese return BOOT_DEVICE_SPI; 49a5f88877SStefan Roese }; 50a5f88877SStefan Roese } 51a5f88877SStefan Roese spl_boot_device(void)52a5f88877SStefan Roeseu32 spl_boot_device(void) 53a5f88877SStefan Roese { 54a5f88877SStefan Roese return get_boot_device(); 55350b50eeSStefan Roese } 56350b50eeSStefan Roese 578ed43b96SStefan Roese #ifdef CONFIG_SPL_MMC_SUPPORT spl_boot_mode(const u32 boot_device)58*2b1cdafaSMarek Vasutu32 spl_boot_mode(const u32 boot_device) 598ed43b96SStefan Roese { 608ed43b96SStefan Roese return MMCSD_MODE_RAW; 618ed43b96SStefan Roese } 628ed43b96SStefan Roese #endif 638ed43b96SStefan Roese board_init_f(ulong dummy)64350b50eeSStefan Roesevoid board_init_f(ulong dummy) 65350b50eeSStefan Roese { 666451223aSStefan Roese int ret; 676451223aSStefan Roese 68e3cccf9eSStefan Roese /* 69e3cccf9eSStefan Roese * Pin muxing needs to be done before UART output, since 70e3cccf9eSStefan Roese * on A38x the UART pins need some re-muxing for output 71e3cccf9eSStefan Roese * to work. 72e3cccf9eSStefan Roese */ 73e3cccf9eSStefan Roese board_early_init_f(); 74e3cccf9eSStefan Roese 756451223aSStefan Roese /* Example code showing how to enable the debug UART on MVEBU */ 766451223aSStefan Roese #ifdef EARLY_UART 776451223aSStefan Roese /* 786451223aSStefan Roese * Debug UART can be used from here if required: 796451223aSStefan Roese * 806451223aSStefan Roese * debug_uart_init(); 816451223aSStefan Roese * printch('a'); 826451223aSStefan Roese * printhex8(0x1234); 836451223aSStefan Roese * printascii("string"); 846451223aSStefan Roese */ 856451223aSStefan Roese #endif 866451223aSStefan Roese 876451223aSStefan Roese ret = spl_init(); 886451223aSStefan Roese if (ret) { 896451223aSStefan Roese debug("spl_init() failed: %d\n", ret); 906451223aSStefan Roese hang(); 916451223aSStefan Roese } 926451223aSStefan Roese 936451223aSStefan Roese /* Use special translation offset for SPL */ 946451223aSStefan Roese dm_set_translation_offset(0xd0000000 - 0xf1000000); 956451223aSStefan Roese 96350b50eeSStefan Roese preloader_console_init(); 97350b50eeSStefan Roese 98ade741b3SStefan Roese timer_init(); 99ade741b3SStefan Roese 10009e89ab4SStefan Roese /* Armada 375 does not support SerDes and DDR3 init yet */ 10109e89ab4SStefan Roese #if !defined(CONFIG_ARMADA_375) 102350b50eeSStefan Roese /* First init the serdes PHY's */ 103350b50eeSStefan Roese serdes_phy_config(); 104350b50eeSStefan Roese 105350b50eeSStefan Roese /* Setup DDR */ 106350b50eeSStefan Roese ddr3_init(); 10709e89ab4SStefan Roese #endif 108350b50eeSStefan Roese 109944c7a31SStefan Roese /* 110944c7a31SStefan Roese * Return to the BootROM to continue the Marvell xmodem 111944c7a31SStefan Roese * UART boot protocol. As initiated by the kwboot tool. 112944c7a31SStefan Roese * 113944c7a31SStefan Roese * This can only be done by the BootROM and not by the 114944c7a31SStefan Roese * U-Boot SPL infrastructure, since the beginning of the 115944c7a31SStefan Roese * image is already read and interpreted by the BootROM. 116944c7a31SStefan Roese * SPL has no chance to receive this information. So we 117944c7a31SStefan Roese * need to return to the BootROM to enable this xmodem 118944c7a31SStefan Roese * UART download. 119944c7a31SStefan Roese */ 120f4db6c97SStefan Roese if (get_boot_device() == BOOT_DEVICE_UART) 121944c7a31SStefan Roese return_to_bootrom(); 122350b50eeSStefan Roese } 123