1edb47025SStefan Roese /* 2edb47025SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 3edb47025SStefan Roese * 4edb47025SStefan Roese * SPDX-License-Identifier: GPL-2.0 5edb47025SStefan Roese */ 6edb47025SStefan Roese 7edb47025SStefan Roese #ifndef _CTRL_PEX_H 8edb47025SStefan Roese #define _CTRL_PEX_H 9edb47025SStefan Roese 10edb47025SStefan Roese #include "high_speed_env_spec.h" 11edb47025SStefan Roese 12edb47025SStefan Roese /* Sample at Reset */ 13edb47025SStefan Roese #define MPP_SAMPLE_AT_RESET(id) (0xe4200 + (id * 4)) 14edb47025SStefan Roese 15edb47025SStefan Roese /* PCI Express Control and Status Registers */ 16edb47025SStefan Roese #define MAX_PEX_BUSSES 256 17edb47025SStefan Roese 18edb47025SStefan Roese #define MISC_REGS_OFFSET 0x18200 19edb47025SStefan Roese #define MV_MISC_REGS_BASE MISC_REGS_OFFSET 20edb47025SStefan Roese #define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4) 21edb47025SStefan Roese 22ad6ac7aaSStefan Roese #define PEX_IF_REGS_OFFSET(if) ((if) > 0 ? \ 23ad6ac7aaSStefan Roese (0x40000 + ((if) - 1) * 0x4000) : \ 24ad6ac7aaSStefan Roese 0x80000) 25ad6ac7aaSStefan Roese #define PEX_IF_REGS_BASE(if) (PEX_IF_REGS_OFFSET(if)) 26edb47025SStefan Roese #define PEX_CAPABILITIES_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x60) 27edb47025SStefan Roese #define PEX_LINK_CTRL_STATUS2_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x90) 28edb47025SStefan Roese #define PEX_CTRL_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a00) 29edb47025SStefan Roese #define PEX_STATUS_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a04) 30edb47025SStefan Roese #define PEX_DBG_STATUS_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a64) 31edb47025SStefan Roese #define PEX_LINK_CAPABILITY_REG 0x6c 32edb47025SStefan Roese #define PEX_LINK_CTRL_STAT_REG 0x70 33edb47025SStefan Roese #define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */ 34edb47025SStefan Roese #define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) 35edb47025SStefan Roese #define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */ 36edb47025SStefan Roese #define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS) 37edb47025SStefan Roese 38edb47025SStefan Roese /* PEX_CAPABILITIES_REG fields */ 39edb47025SStefan Roese #define PCIE0_ENABLE_OFFS 0 40edb47025SStefan Roese #define PCIE0_ENABLE_MASK (0x1 << PCIE0_ENABLE_OFFS) 41edb47025SStefan Roese #define PCIE1_ENABLE_OFFS 1 42edb47025SStefan Roese #define PCIE1_ENABLE_MASK (0x1 << PCIE1_ENABLE_OFFS) 43edb47025SStefan Roese #define PCIE2_ENABLE_OFFS 2 44edb47025SStefan Roese #define PCIE2_ENABLE_MASK (0x1 << PCIE2_ENABLE_OFFS) 45edb47025SStefan Roese #define PCIE3_ENABLE_OFFS 3 46edb47025SStefan Roese #define PCIE4_ENABLE_MASK (0x1 << PCIE3_ENABLE_OFFS) 47edb47025SStefan Roese 48edb47025SStefan Roese /* Controller revision info */ 49edb47025SStefan Roese #define PEX_DEVICE_AND_VENDOR_ID 0x000 50edb47025SStefan Roese 51edb47025SStefan Roese /* PCI Express Configuration Address Register */ 52edb47025SStefan Roese #define PXCAR_REG_NUM_OFFS 2 53edb47025SStefan Roese #define PXCAR_REG_NUM_MAX 0x3f 54edb47025SStefan Roese #define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << \ 55edb47025SStefan Roese PXCAR_REG_NUM_OFFS) 56edb47025SStefan Roese #define PXCAR_FUNC_NUM_OFFS 8 57edb47025SStefan Roese #define PXCAR_FUNC_NUM_MAX 0x7 58edb47025SStefan Roese #define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << \ 59edb47025SStefan Roese PXCAR_FUNC_NUM_OFFS) 60edb47025SStefan Roese #define PXCAR_DEVICE_NUM_OFFS 11 61edb47025SStefan Roese #define PXCAR_DEVICE_NUM_MAX 0x1f 62edb47025SStefan Roese #define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << \ 63edb47025SStefan Roese PXCAR_DEVICE_NUM_OFFS) 64edb47025SStefan Roese #define PXCAR_BUS_NUM_OFFS 16 65edb47025SStefan Roese #define PXCAR_BUS_NUM_MAX 0xff 66edb47025SStefan Roese #define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << \ 67edb47025SStefan Roese PXCAR_BUS_NUM_OFFS) 68edb47025SStefan Roese #define PXCAR_EXT_REG_NUM_OFFS 24 69edb47025SStefan Roese #define PXCAR_EXT_REG_NUM_MAX 0xf 70edb47025SStefan Roese 71edb47025SStefan Roese #define PEX_CFG_ADDR_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x18f8) 72edb47025SStefan Roese #define PEX_CFG_DATA_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x18fc) 73edb47025SStefan Roese 74edb47025SStefan Roese #define PXCAR_REAL_EXT_REG_NUM_OFFS 8 75edb47025SStefan Roese #define PXCAR_REAL_EXT_REG_NUM_MASK (0xf << PXCAR_REAL_EXT_REG_NUM_OFFS) 76edb47025SStefan Roese 77edb47025SStefan Roese #define PXCAR_CONFIG_EN BIT(31) 78edb47025SStefan Roese #define PEX_STATUS_AND_COMMAND 0x004 79edb47025SStefan Roese #define PXSAC_MABORT BIT(29) /* Recieved Master Abort */ 80edb47025SStefan Roese 81490753acSKevin Smith int hws_pex_config(const struct serdes_map *serdes_map, u8 count); 82edb47025SStefan Roese int pex_local_bus_num_set(u32 pex_if, u32 bus_num); 83edb47025SStefan Roese int pex_local_dev_num_set(u32 pex_if, u32 dev_num); 84edb47025SStefan Roese u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off); 85edb47025SStefan Roese 86*2ad43094SMario Six void board_pex_config(void); 87*2ad43094SMario Six 88edb47025SStefan Roese #endif 89