18cb78722SStefan Roese /* 28cb78722SStefan Roese * (C) Copyright 2009 38cb78722SStefan Roese * Marvell Semiconductor <www.marvell.com> 48cb78722SStefan Roese * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 58cb78722SStefan Roese * 68cb78722SStefan Roese * Header file for the Marvell's Feroceon CPU core. 78cb78722SStefan Roese * 88cb78722SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 98cb78722SStefan Roese */ 108cb78722SStefan Roese 11*250eea74SStefan Roese #ifndef _MVEBU_SOC_H 12*250eea74SStefan Roese #define _MVEBU_SOC_H 138cb78722SStefan Roese 148cb78722SStefan Roese #define SOC_MV78460_ID 0x7846 158cb78722SStefan Roese 168cb78722SStefan Roese /* TCLK Core Clock definition */ 178cb78722SStefan Roese #ifndef CONFIG_SYS_TCLK 188cb78722SStefan Roese #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 198cb78722SStefan Roese #endif 208cb78722SStefan Roese 218cb78722SStefan Roese /* SOC specific definations */ 228cb78722SStefan Roese #define INTREG_BASE 0xd0000000 238cb78722SStefan Roese #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) 248cb78722SStefan Roese #define SOC_REGS_PHY_BASE 0xf1000000 258cb78722SStefan Roese #define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x) 268cb78722SStefan Roese 278cb78722SStefan Roese #define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504)) 288cb78722SStefan Roese #define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600)) 298cb78722SStefan Roese #define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) 308cb78722SStefan Roese #define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000)) 318cb78722SStefan Roese #define MVEBU_UART1_BASE (MVEBU_REGISTER(0x12100)) 328cb78722SStefan Roese #define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000)) 338cb78722SStefan Roese #define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100)) 348cb78722SStefan Roese #define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140)) 358cb78722SStefan Roese #define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180)) 368cb78722SStefan Roese #define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200)) 378cb78722SStefan Roese #define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000)) 388cb78722SStefan Roese #define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180)) 398cb78722SStefan Roese #define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300)) 408cb78722SStefan Roese #define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000)) 418cb78722SStefan Roese #define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000)) 428cb78722SStefan Roese #define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000)) 438cb78722SStefan Roese #define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000)) 448cb78722SStefan Roese #define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000)) 458cb78722SStefan Roese 468cb78722SStefan Roese #define SDRAM_MAX_CS 4 478cb78722SStefan Roese #define SDRAM_ADDR_MASK 0xFF000000 488cb78722SStefan Roese 498cb78722SStefan Roese /* Armada XP GbE controller has 4 ports */ 508cb78722SStefan Roese #define MAX_MVNETA_DEVS 4 518cb78722SStefan Roese 52*250eea74SStefan Roese /* MVEBU CPU memory windows */ 538cb78722SStefan Roese #define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA 548cb78722SStefan Roese #define MVCPU_WIN_ENABLE CPU_WIN_ENABLE 558cb78722SStefan Roese #define MVCPU_WIN_DISABLE CPU_WIN_DISABLE 568cb78722SStefan Roese 57*250eea74SStefan Roese #endif /* _MVEBU_SOC_H */ 58