18cb78722SStefan Roese /* 28cb78722SStefan Roese * (C) Copyright 2009 38cb78722SStefan Roese * Marvell Semiconductor <www.marvell.com> 48cb78722SStefan Roese * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 58cb78722SStefan Roese * 68cb78722SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 78cb78722SStefan Roese */ 88cb78722SStefan Roese 9250eea74SStefan Roese #ifndef _MVEBU_CPU_H 10250eea74SStefan Roese #define _MVEBU_CPU_H 118cb78722SStefan Roese 128cb78722SStefan Roese #include <asm/system.h> 138cb78722SStefan Roese 148cb78722SStefan Roese #ifndef __ASSEMBLY__ 158cb78722SStefan Roese 168cb78722SStefan Roese #define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00) 178cb78722SStefan Roese #define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08) 188cb78722SStefan Roese 198cb78722SStefan Roese enum memory_bank { 208cb78722SStefan Roese BANK0, 218cb78722SStefan Roese BANK1, 228cb78722SStefan Roese BANK2, 238cb78722SStefan Roese BANK3 248cb78722SStefan Roese }; 258cb78722SStefan Roese 268cb78722SStefan Roese enum cpu_winen { 278cb78722SStefan Roese CPU_WIN_DISABLE, 288cb78722SStefan Roese CPU_WIN_ENABLE 298cb78722SStefan Roese }; 308cb78722SStefan Roese 318cb78722SStefan Roese enum cpu_target { 328cb78722SStefan Roese CPU_TARGET_DRAM = 0x0, 338cb78722SStefan Roese CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1, 348cb78722SStefan Roese CPU_TARGET_ETH23 = 0x3, 358cb78722SStefan Roese CPU_TARGET_PCIE02 = 0x4, 368cb78722SStefan Roese CPU_TARGET_ETH01 = 0x7, 378cb78722SStefan Roese CPU_TARGET_PCIE13 = 0x8, 388cb78722SStefan Roese CPU_TARGET_SASRAM = 0x9, 398cb78722SStefan Roese CPU_TARGET_NAND = 0xd, 408cb78722SStefan Roese }; 418cb78722SStefan Roese 428cb78722SStefan Roese enum cpu_attrib { 438cb78722SStefan Roese CPU_ATTR_SASRAM = 0x01, 448cb78722SStefan Roese CPU_ATTR_DRAM_CS0 = 0x0e, 458cb78722SStefan Roese CPU_ATTR_DRAM_CS1 = 0x0d, 468cb78722SStefan Roese CPU_ATTR_DRAM_CS2 = 0x0b, 478cb78722SStefan Roese CPU_ATTR_DRAM_CS3 = 0x07, 488cb78722SStefan Roese CPU_ATTR_NANDFLASH = 0x2f, 498cb78722SStefan Roese CPU_ATTR_SPIFLASH = 0x1e, 508cb78722SStefan Roese CPU_ATTR_BOOTROM = 0x1d, 518cb78722SStefan Roese CPU_ATTR_PCIE_IO = 0xe0, 528cb78722SStefan Roese CPU_ATTR_PCIE_MEM = 0xe8, 538cb78722SStefan Roese CPU_ATTR_DEV_CS0 = 0x3e, 548cb78722SStefan Roese CPU_ATTR_DEV_CS1 = 0x3d, 558cb78722SStefan Roese CPU_ATTR_DEV_CS2 = 0x3b, 568cb78722SStefan Roese CPU_ATTR_DEV_CS3 = 0x37, 578cb78722SStefan Roese }; 588cb78722SStefan Roese 599c6d3b7bSStefan Roese enum { 609c6d3b7bSStefan Roese MVEBU_SOC_AXP, 619c6d3b7bSStefan Roese MVEBU_SOC_A38X, 629c6d3b7bSStefan Roese MVEBU_SOC_UNKNOWN, 639c6d3b7bSStefan Roese }; 649c6d3b7bSStefan Roese 658cb78722SStefan Roese /* 668cb78722SStefan Roese * Default Device Address MAP BAR values 678cb78722SStefan Roese */ 688ed20d65SStefan Roese #define MBUS_PCI_MEM_BASE 0xE8000000 698ed20d65SStefan Roese #define MBUS_PCI_MEM_SIZE (128 << 20) 708ed20d65SStefan Roese #define MBUS_PCI_IO_BASE 0xF1100000 718ed20d65SStefan Roese #define MBUS_PCI_IO_SIZE (64 << 10) 728ed20d65SStefan Roese #define MBUS_SPI_BASE 0xF4000000 738ed20d65SStefan Roese #define MBUS_SPI_SIZE (8 << 20) 748ed20d65SStefan Roese #define MBUS_BOOTROM_BASE 0xF8000000 758ed20d65SStefan Roese #define MBUS_BOOTROM_SIZE (8 << 20) 768cb78722SStefan Roese 778cb78722SStefan Roese struct mbus_win { 788cb78722SStefan Roese u32 base; 798cb78722SStefan Roese u32 size; 808cb78722SStefan Roese u8 target; 818cb78722SStefan Roese u8 attr; 828cb78722SStefan Roese }; 838cb78722SStefan Roese 848cb78722SStefan Roese /* 858cb78722SStefan Roese * System registers 868cb78722SStefan Roese * Ref: Datasheet sec:A.28 878cb78722SStefan Roese */ 888cb78722SStefan Roese struct mvebu_system_registers { 898cb78722SStefan Roese u8 pad1[0x60]; 908cb78722SStefan Roese u32 rstoutn_mask; /* 0x60 */ 918cb78722SStefan Roese u32 sys_soft_rst; /* 0x64 */ 928cb78722SStefan Roese }; 938cb78722SStefan Roese 948cb78722SStefan Roese /* 958cb78722SStefan Roese * GPIO Registers 968cb78722SStefan Roese * Ref: Datasheet sec:A.19 978cb78722SStefan Roese */ 988cb78722SStefan Roese struct kwgpio_registers { 998cb78722SStefan Roese u32 dout; 1008cb78722SStefan Roese u32 oe; 1018cb78722SStefan Roese u32 blink_en; 1028cb78722SStefan Roese u32 din_pol; 1038cb78722SStefan Roese u32 din; 1048cb78722SStefan Roese u32 irq_cause; 1058cb78722SStefan Roese u32 irq_mask; 1068cb78722SStefan Roese u32 irq_level; 1078cb78722SStefan Roese }; 1088cb78722SStefan Roese 1098cb78722SStefan Roese /* Needed for dynamic (board-specific) mbus configuration */ 1108cb78722SStefan Roese extern struct mvebu_mbus_state mbus_state; 1118cb78722SStefan Roese 1128cb78722SStefan Roese /* 1138cb78722SStefan Roese * functions 1148cb78722SStefan Roese */ 1158cb78722SStefan Roese unsigned int mvebu_sdram_bar(enum memory_bank bank); 1168cb78722SStefan Roese unsigned int mvebu_sdram_bs(enum memory_bank bank); 1178cb78722SStefan Roese void mvebu_sdram_size_adjust(enum memory_bank bank); 1188cb78722SStefan Roese int mvebu_mbus_probe(struct mbus_win windows[], int count); 1199c6d3b7bSStefan Roese int mvebu_soc_family(void); 120*2a0b7dc3SStefan Roese u32 mvebu_get_nand_clock(void); 1218cb78722SStefan Roese 1227f1adcd7SStefan Roese int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks); 1237f1adcd7SStefan Roese 1248cb78722SStefan Roese /* 1258cb78722SStefan Roese * Highspeed SERDES PHY config init, ported from bin_hdr 1268cb78722SStefan Roese * to mainline U-Boot 1278cb78722SStefan Roese */ 1288cb78722SStefan Roese int serdes_phy_config(void); 1298cb78722SStefan Roese 1308cb78722SStefan Roese /* 1318cb78722SStefan Roese * DDR3 init / training code ported from Marvell bin_hdr. Now 1328cb78722SStefan Roese * available in mainline U-Boot in: 133ff9112dfSStefan Roese * drivers/ddr/marvell 1348cb78722SStefan Roese */ 1358cb78722SStefan Roese int ddr3_init(void); 1368cb78722SStefan Roese #endif /* __ASSEMBLY__ */ 137250eea74SStefan Roese #endif /* _MVEBU_CPU_H */ 138