18cb78722SStefan Roese /* 28cb78722SStefan Roese * (C) Copyright 2011 38cb78722SStefan Roese * Marvell Semiconductor <www.marvell.com> 48cb78722SStefan Roese * Written-by: Lei Wen <leiwen@marvell.com> 58cb78722SStefan Roese * 68cb78722SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 78cb78722SStefan Roese */ 88cb78722SStefan Roese 98cb78722SStefan Roese /* 108cb78722SStefan Roese * This file should be included in board config header file. 118cb78722SStefan Roese * 128cb78722SStefan Roese * It supports common definitions for Armada XP platforms 138cb78722SStefan Roese */ 148cb78722SStefan Roese 15*250eea74SStefan Roese #ifndef _MVEBU_CONFIG_H 16*250eea74SStefan Roese #define _MVEBU_CONFIG_H 178cb78722SStefan Roese 188cb78722SStefan Roese #include <asm/arch/soc.h> 198cb78722SStefan Roese 208cb78722SStefan Roese #define MV88F78X60 /* for the DDR training bin_hdr code */ 218cb78722SStefan Roese 228cb78722SStefan Roese #define CONFIG_SYS_CACHELINE_SIZE 32 238cb78722SStefan Roese 248cb78722SStefan Roese /* 258cb78722SStefan Roese * By default kwbimage.cfg from board specific folder is used 268cb78722SStefan Roese * If for some board, different configuration file need to be used, 278cb78722SStefan Roese * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file 288cb78722SStefan Roese */ 298cb78722SStefan Roese #ifndef CONFIG_SYS_KWD_CONFIG 308cb78722SStefan Roese #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg 318cb78722SStefan Roese #endif /* CONFIG_SYS_KWD_CONFIG */ 328cb78722SStefan Roese 338cb78722SStefan Roese /* Add target to build it automatically upon "make" */ 348cb78722SStefan Roese #ifdef CONFIG_SPL 358cb78722SStefan Roese #define CONFIG_BUILD_TARGET "u-boot-spl.kwb" 368cb78722SStefan Roese #else 378cb78722SStefan Roese #define CONFIG_BUILD_TARGET "u-boot.kwb" 388cb78722SStefan Roese #endif 398cb78722SStefan Roese 408cb78722SStefan Roese /* end of 16M scrubbed by training in bootrom */ 418cb78722SStefan Roese #define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000 428cb78722SStefan Roese #define CONFIG_NR_DRAM_BANKS_MAX 2 438cb78722SStefan Roese 448cb78722SStefan Roese #define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE 458cb78722SStefan Roese 468cb78722SStefan Roese /* 478cb78722SStefan Roese * SPI Flash configuration 488cb78722SStefan Roese */ 498cb78722SStefan Roese #ifdef CONFIG_CMD_SF 508cb78722SStefan Roese #define CONFIG_HARD_SPI 1 518cb78722SStefan Roese #define CONFIG_KIRKWOOD_SPI 1 528cb78722SStefan Roese #ifndef CONFIG_ENV_SPI_BUS 538cb78722SStefan Roese # define CONFIG_ENV_SPI_BUS 0 548cb78722SStefan Roese #endif 558cb78722SStefan Roese #ifndef CONFIG_ENV_SPI_CS 568cb78722SStefan Roese # define CONFIG_ENV_SPI_CS 0 578cb78722SStefan Roese #endif 588cb78722SStefan Roese #ifndef CONFIG_ENV_SPI_MAX_HZ 598cb78722SStefan Roese # define CONFIG_ENV_SPI_MAX_HZ 50000000 608cb78722SStefan Roese #endif 618cb78722SStefan Roese #endif 628cb78722SStefan Roese 638cb78722SStefan Roese /* 648cb78722SStefan Roese * Ethernet Driver configuration 658cb78722SStefan Roese */ 668cb78722SStefan Roese #ifdef CONFIG_CMD_NET 678cb78722SStefan Roese #define CONFIG_CMD_MII 688cb78722SStefan Roese #define CONFIG_MII /* expose smi ove miiphy interface */ 698cb78722SStefan Roese #define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */ 708cb78722SStefan Roese #define CONFIG_PHYLIB 718cb78722SStefan Roese #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 728cb78722SStefan Roese #define CONFIG_PHY_GIGE /* GbE speed/duplex detect */ 738cb78722SStefan Roese #endif /* CONFIG_CMD_NET */ 748cb78722SStefan Roese 758cb78722SStefan Roese /* 768cb78722SStefan Roese * I2C related stuff 778cb78722SStefan Roese */ 788cb78722SStefan Roese #ifdef CONFIG_CMD_I2C 798cb78722SStefan Roese #ifndef CONFIG_SYS_I2C_SOFT 808cb78722SStefan Roese #define CONFIG_I2C_MVTWSI 818cb78722SStefan Roese #endif 828cb78722SStefan Roese #define CONFIG_SYS_I2C_SLAVE 0x0 838cb78722SStefan Roese #define CONFIG_SYS_I2C_SPEED 100000 848cb78722SStefan Roese #endif 858cb78722SStefan Roese 86*250eea74SStefan Roese #endif /* __MVEBU_CONFIG_H */ 87