18cb78722SStefan Roese /* 28cb78722SStefan Roese * (C) Copyright 2011 38cb78722SStefan Roese * Marvell Semiconductor <www.marvell.com> 48cb78722SStefan Roese * Written-by: Lei Wen <leiwen@marvell.com> 58cb78722SStefan Roese * 68cb78722SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 78cb78722SStefan Roese */ 88cb78722SStefan Roese 98cb78722SStefan Roese /* 108cb78722SStefan Roese * This file should be included in board config header file. 118cb78722SStefan Roese * 12f7c0ef07SStefan Roese * It supports common definitions for MVEBU platforms 138cb78722SStefan Roese */ 148cb78722SStefan Roese 15250eea74SStefan Roese #ifndef _MVEBU_CONFIG_H 16250eea74SStefan Roese #define _MVEBU_CONFIG_H 178cb78722SStefan Roese 188cb78722SStefan Roese #include <asm/arch/soc.h> 198cb78722SStefan Roese 20*09e89ab4SStefan Roese #if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_375) \ 21*09e89ab4SStefan Roese || defined(CONFIG_ARMADA_38X) 2281e33f4bSStefan Roese /* 2381e33f4bSStefan Roese * Set this for the common xor register definitions needed in dram.c 2481e33f4bSStefan Roese * for A38x as well here. 2581e33f4bSStefan Roese */ 268cb78722SStefan Roese #define MV88F78X60 /* for the DDR training bin_hdr code */ 27f7c0ef07SStefan Roese #endif 288cb78722SStefan Roese 298a02ec1dSStefan Roese #define CONFIG_SYS_L2_PL310 308a02ec1dSStefan Roese 318a02ec1dSStefan Roese #ifdef CONFIG_SPL_BUILD 328a02ec1dSStefan Roese #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ 338a02ec1dSStefan Roese #endif 348a02ec1dSStefan Roese 358cb78722SStefan Roese /* 368cb78722SStefan Roese * By default kwbimage.cfg from board specific folder is used 378cb78722SStefan Roese * If for some board, different configuration file need to be used, 388cb78722SStefan Roese * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file 398cb78722SStefan Roese */ 408cb78722SStefan Roese #ifndef CONFIG_SYS_KWD_CONFIG 418cb78722SStefan Roese #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg 428cb78722SStefan Roese #endif /* CONFIG_SYS_KWD_CONFIG */ 438cb78722SStefan Roese 448cb78722SStefan Roese /* Add target to build it automatically upon "make" */ 458cb78722SStefan Roese #ifdef CONFIG_SPL 468cb78722SStefan Roese #define CONFIG_BUILD_TARGET "u-boot-spl.kwb" 478cb78722SStefan Roese #endif 488cb78722SStefan Roese 498cb78722SStefan Roese /* end of 16M scrubbed by training in bootrom */ 508cb78722SStefan Roese #define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000 518cb78722SStefan Roese #define CONFIG_NR_DRAM_BANKS_MAX 2 528cb78722SStefan Roese 538cb78722SStefan Roese #define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE 548cb78722SStefan Roese 558cb78722SStefan Roese /* 568cb78722SStefan Roese * SPI Flash configuration 578cb78722SStefan Roese */ 588cb78722SStefan Roese #ifdef CONFIG_CMD_SF 598cb78722SStefan Roese #ifndef CONFIG_ENV_SPI_BUS 608cb78722SStefan Roese # define CONFIG_ENV_SPI_BUS 0 618cb78722SStefan Roese #endif 628cb78722SStefan Roese #ifndef CONFIG_ENV_SPI_CS 638cb78722SStefan Roese # define CONFIG_ENV_SPI_CS 0 648cb78722SStefan Roese #endif 658cb78722SStefan Roese #ifndef CONFIG_ENV_SPI_MAX_HZ 668cb78722SStefan Roese # define CONFIG_ENV_SPI_MAX_HZ 50000000 678cb78722SStefan Roese #endif 688cb78722SStefan Roese #endif 698cb78722SStefan Roese 7009a54c00SStefan Roese /* Needed for SPI NOR booting in SPL */ 7109a54c00SStefan Roese #define CONFIG_DM_SEQ_ALIAS 1 7209a54c00SStefan Roese 738cb78722SStefan Roese /* 748cb78722SStefan Roese * Ethernet Driver configuration 758cb78722SStefan Roese */ 768cb78722SStefan Roese #ifdef CONFIG_CMD_NET 778cb78722SStefan Roese #define CONFIG_MII /* expose smi ove miiphy interface */ 78*09e89ab4SStefan Roese #if !defined(CONFIG_ARMADA_375) 798cb78722SStefan Roese #define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */ 80*09e89ab4SStefan Roese #endif 818cb78722SStefan Roese #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 829eb14cc4SStefan Roese #define CONFIG_ARP_TIMEOUT 200 839eb14cc4SStefan Roese #define CONFIG_NET_RETRY_COUNT 50 848cb78722SStefan Roese #endif /* CONFIG_CMD_NET */ 858cb78722SStefan Roese 868cb78722SStefan Roese /* 878cb78722SStefan Roese * I2C related stuff 888cb78722SStefan Roese */ 898cb78722SStefan Roese #ifdef CONFIG_CMD_I2C 908cb78722SStefan Roese #ifndef CONFIG_SYS_I2C_SOFT 918cb78722SStefan Roese #define CONFIG_I2C_MVTWSI 928cb78722SStefan Roese #endif 938cb78722SStefan Roese #define CONFIG_SYS_I2C_SLAVE 0x0 948cb78722SStefan Roese #define CONFIG_SYS_I2C_SPEED 100000 958cb78722SStefan Roese #endif 968cb78722SStefan Roese 972fbc18feSStefan Roese /* Use common timer */ 982fbc18feSStefan Roese #define CONFIG_SYS_TIMER_COUNTS_DOWN 992fbc18feSStefan Roese #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) 1002fbc18feSStefan Roese #define CONFIG_SYS_TIMER_RATE 25000000 1012fbc18feSStefan Roese 102250eea74SStefan Roese #endif /* __MVEBU_CONFIG_H */ 103