1*d0787656SStefan Roese /*
2*d0787656SStefan Roese * (C) Copyright 2009
3*d0787656SStefan Roese * Marvell Semiconductor <www.marvell.com>
4*d0787656SStefan Roese * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5*d0787656SStefan Roese *
6*d0787656SStefan Roese * SPDX-License-Identifier: GPL-2.0+
7*d0787656SStefan Roese */
8*d0787656SStefan Roese
9*d0787656SStefan Roese #include <common.h>
10*d0787656SStefan Roese #include <asm/io.h>
11*d0787656SStefan Roese #include <asm/arch/cpu.h>
12*d0787656SStefan Roese #include <asm/arch/soc.h>
13*d0787656SStefan Roese
14*d0787656SStefan Roese /*
15*d0787656SStefan Roese * mvebu_config_gpio - GPIO configuration
16*d0787656SStefan Roese */
mvebu_config_gpio(u32 gpp0_oe_val,u32 gpp1_oe_val,u32 gpp0_oe,u32 gpp1_oe)17*d0787656SStefan Roese void mvebu_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val,
18*d0787656SStefan Roese u32 gpp0_oe, u32 gpp1_oe)
19*d0787656SStefan Roese {
20*d0787656SStefan Roese struct kwgpio_registers *gpio0reg =
21*d0787656SStefan Roese (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
22*d0787656SStefan Roese struct kwgpio_registers *gpio1reg =
23*d0787656SStefan Roese (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
24*d0787656SStefan Roese
25*d0787656SStefan Roese /* Init GPIOS to default values as per board requirement */
26*d0787656SStefan Roese writel(gpp0_oe_val, &gpio0reg->dout);
27*d0787656SStefan Roese writel(gpp1_oe_val, &gpio1reg->dout);
28*d0787656SStefan Roese writel(gpp0_oe, &gpio0reg->oe);
29*d0787656SStefan Roese writel(gpp1_oe, &gpio1reg->oe);
30*d0787656SStefan Roese }
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