xref: /rk3399_rockchip-uboot/arch/arm/mach-mvebu/arm64-common.c (revision 0e00a84cdedf7a1949486746225b35984b351eca)
121b29fc6SStefan Roese /*
221b29fc6SStefan Roese  * Copyright (C) 2016 Stefan Roese <sr@denx.de>
321b29fc6SStefan Roese  *
421b29fc6SStefan Roese  * SPDX-License-Identifier:	GPL-2.0+
521b29fc6SStefan Roese  */
621b29fc6SStefan Roese 
721b29fc6SStefan Roese #include <common.h>
821b29fc6SStefan Roese #include <dm.h>
921b29fc6SStefan Roese #include <fdtdec.h>
10*0e00a84cSMasahiro Yamada #include <linux/libfdt.h>
11f4f194e8SKonstantin Porotchkin #include <pci.h>
1221b29fc6SStefan Roese #include <asm/io.h>
1321b29fc6SStefan Roese #include <asm/system.h>
1421b29fc6SStefan Roese #include <asm/arch/cpu.h>
1521b29fc6SStefan Roese #include <asm/arch/soc.h>
1621b29fc6SStefan Roese #include <asm/armv8/mmu.h>
1721b29fc6SStefan Roese 
1821b29fc6SStefan Roese DECLARE_GLOBAL_DATA_PTR;
1921b29fc6SStefan Roese 
2021b29fc6SStefan Roese /*
21059f75d5SStefan Roese  * Not all memory is mapped in the MMU. So we need to restrict the
22059f75d5SStefan Roese  * memory size so that U-Boot does not try to access it. Also, the
23059f75d5SStefan Roese  * internal registers are located at 0xf000.0000 - 0xffff.ffff.
24059f75d5SStefan Roese  * Currently only 2GiB are mapped for system memory. This is what
25059f75d5SStefan Roese  * we pass to the U-Boot subsystem here.
26059f75d5SStefan Roese  */
27059f75d5SStefan Roese #define USABLE_RAM_SIZE		0x80000000
28059f75d5SStefan Roese 
board_get_usable_ram_top(ulong total_size)29059f75d5SStefan Roese ulong board_get_usable_ram_top(ulong total_size)
30059f75d5SStefan Roese {
31059f75d5SStefan Roese 	if (gd->ram_size > USABLE_RAM_SIZE)
32059f75d5SStefan Roese 		return USABLE_RAM_SIZE;
33059f75d5SStefan Roese 
34059f75d5SStefan Roese 	return gd->ram_size;
35059f75d5SStefan Roese }
36059f75d5SStefan Roese 
37059f75d5SStefan Roese /*
3821b29fc6SStefan Roese  * On ARMv8, MBus is not configured in U-Boot. To enable compilation
3921b29fc6SStefan Roese  * of the already implemented drivers, lets add a dummy version of
4021b29fc6SStefan Roese  * this function so that linking does not fail.
4121b29fc6SStefan Roese  */
mvebu_mbus_dram_info(void)4221b29fc6SStefan Roese const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
4321b29fc6SStefan Roese {
4421b29fc6SStefan Roese 	return NULL;
4521b29fc6SStefan Roese }
4621b29fc6SStefan Roese 
4721b29fc6SStefan Roese /* DRAM init code ... */
4821b29fc6SStefan Roese 
dram_init_banksize(void)49780f80cdSStefan Roese int dram_init_banksize(void)
5021b29fc6SStefan Roese {
51780f80cdSStefan Roese 	fdtdec_setup_memory_banksize();
5221b29fc6SStefan Roese 
5321b29fc6SStefan Roese 	return 0;
5421b29fc6SStefan Roese }
5521b29fc6SStefan Roese 
dram_init(void)56780f80cdSStefan Roese int dram_init(void)
5721b29fc6SStefan Roese {
58780f80cdSStefan Roese 	if (fdtdec_setup_memory_size() != 0)
59780f80cdSStefan Roese 		return -EINVAL;
6076b00acaSSimon Glass 
6176b00acaSSimon Glass 	return 0;
6221b29fc6SStefan Roese }
6321b29fc6SStefan Roese 
arch_cpu_init(void)6421b29fc6SStefan Roese int arch_cpu_init(void)
6521b29fc6SStefan Roese {
6621b29fc6SStefan Roese 	/* Nothing to do (yet) */
6721b29fc6SStefan Roese 	return 0;
6821b29fc6SStefan Roese }
6921b29fc6SStefan Roese 
arch_early_init_r(void)7021b29fc6SStefan Roese int arch_early_init_r(void)
7121b29fc6SStefan Roese {
7221b29fc6SStefan Roese 	struct udevice *dev;
7321b29fc6SStefan Roese 	int ret;
74d7dd358fSStefan Roese 	int i;
7521b29fc6SStefan Roese 
76d7dd358fSStefan Roese 	/*
77d7dd358fSStefan Roese 	 * Loop over all MISC uclass drivers to call the comphy code
78d7dd358fSStefan Roese 	 * and init all CP110 devices enabled in the DT
79d7dd358fSStefan Roese 	 */
80d7dd358fSStefan Roese 	i = 0;
81d7dd358fSStefan Roese 	while (1) {
8221b29fc6SStefan Roese 		/* Call the comphy code via the MISC uclass driver */
83d7dd358fSStefan Roese 		ret = uclass_get_device(UCLASS_MISC, i++, &dev);
84d7dd358fSStefan Roese 
85d7dd358fSStefan Roese 		/* We're done, once no further CP110 device is found */
86d7dd358fSStefan Roese 		if (ret)
87d7dd358fSStefan Roese 			break;
8821b29fc6SStefan Roese 	}
8921b29fc6SStefan Roese 
9021b29fc6SStefan Roese 	/* Cause the SATA device to do its early init */
9121b29fc6SStefan Roese 	uclass_first_device(UCLASS_AHCI, &dev);
9221b29fc6SStefan Roese 
93f4f194e8SKonstantin Porotchkin #ifdef CONFIG_DM_PCI
94f4f194e8SKonstantin Porotchkin 	/* Trigger PCIe devices detection */
95f4f194e8SKonstantin Porotchkin 	pci_init();
96f4f194e8SKonstantin Porotchkin #endif
97f4f194e8SKonstantin Porotchkin 
9821b29fc6SStefan Roese 	return 0;
9921b29fc6SStefan Roese }
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