1 /* 2 * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <libfdt.h> 9 #include <linux/err.h> 10 #include <asm/arch/gxbb.h> 11 #include <asm/armv8/mmu.h> 12 #include <asm/unaligned.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 int dram_init(void) 17 { 18 const fdt64_t *val; 19 int offset; 20 int len; 21 22 offset = fdt_path_offset(gd->fdt_blob, "/memory"); 23 if (offset < 0) 24 return -EINVAL; 25 26 val = fdt_getprop(gd->fdt_blob, offset, "reg", &len); 27 if (len < sizeof(*val) * 2) 28 return -EINVAL; 29 30 /* Use unaligned access since cache is still disabled */ 31 gd->ram_size = get_unaligned_be64(&val[1]); 32 33 return 0; 34 } 35 36 void dram_init_banksize(void) 37 { 38 /* Reserve first 16 MiB of RAM for firmware */ 39 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024); 40 gd->bd->bi_dram[0].size = gd->ram_size - (16 * 1024 * 1024); 41 } 42 43 void reset_cpu(ulong addr) 44 { 45 psci_system_reset(true); 46 } 47 48 static struct mm_region gxbb_mem_map[] = { 49 { 50 .base = 0x0UL, 51 .size = 0x80000000UL, 52 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 53 PTE_BLOCK_INNER_SHARE 54 }, { 55 .base = 0x80000000UL, 56 .size = 0x80000000UL, 57 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 58 PTE_BLOCK_NON_SHARE | 59 PTE_BLOCK_PXN | PTE_BLOCK_UXN 60 }, { 61 /* List terminator */ 62 0, 63 } 64 }; 65 66 struct mm_region *mem_map = gxbb_mem_map; 67