10fba27b6SVitaly Andrianov /* 20fba27b6SVitaly Andrianov * K2G: SoC definitions 30fba27b6SVitaly Andrianov * 40fba27b6SVitaly Andrianov * (C) Copyright 2015 50fba27b6SVitaly Andrianov * Texas Instruments Incorporated, <www.ti.com> 60fba27b6SVitaly Andrianov * 70fba27b6SVitaly Andrianov * SPDX-License-Identifier: GPL-2.0+ 80fba27b6SVitaly Andrianov */ 90fba27b6SVitaly Andrianov 100fba27b6SVitaly Andrianov #ifndef __ASM_ARCH_HARDWARE_K2G_H 110fba27b6SVitaly Andrianov #define __ASM_ARCH_HARDWARE_K2G_H 120fba27b6SVitaly Andrianov 13*f2a8279eSSuman Anna #define KS2_NUM_DSPS 1 140fba27b6SVitaly Andrianov 150fba27b6SVitaly Andrianov /* Power and Sleep Controller (PSC) Domains */ 160fba27b6SVitaly Andrianov #define KS2_LPSC_ALWAYSON 0 170fba27b6SVitaly Andrianov #define KS2_LPSC_PMMC 1 180fba27b6SVitaly Andrianov #define KS2_LPSC_DEBUG 2 190fba27b6SVitaly Andrianov #define KS2_LPSC_NSS 3 200fba27b6SVitaly Andrianov #define KS2_LPSC_SA 4 210fba27b6SVitaly Andrianov #define KS2_LPSC_TERANET 5 220fba27b6SVitaly Andrianov #define KS2_LPSC_SYS_COMP 6 230fba27b6SVitaly Andrianov #define KS2_LPSC_QSPI 7 240fba27b6SVitaly Andrianov #define KS2_LPSC_MMC 8 250fba27b6SVitaly Andrianov #define KS2_LPSC_GPMC 9 260fba27b6SVitaly Andrianov #define KS2_LPSC_MLB 11 270fba27b6SVitaly Andrianov #define KS2_LPSC_EHRPWM 12 280fba27b6SVitaly Andrianov #define KS2_LPSC_EQEP 13 290fba27b6SVitaly Andrianov #define KS2_LPSC_ECAP 14 300fba27b6SVitaly Andrianov #define KS2_LPSC_MCASP 15 310fba27b6SVitaly Andrianov #define KS2_LPSC_SR 16 320fba27b6SVitaly Andrianov #define KS2_LPSC_MSMC 17 33*f2a8279eSSuman Anna #ifdef KS2_LPSC_GEM_0 34*f2a8279eSSuman Anna #undef KS2_LPSC_GEM_0 35*f2a8279eSSuman Anna #endif 36*f2a8279eSSuman Anna #define KS2_LPSC_GEM_0 18 370fba27b6SVitaly Andrianov #define KS2_LPSC_ARM 19 380fba27b6SVitaly Andrianov #define KS2_LPSC_ASRC 20 390fba27b6SVitaly Andrianov #define KS2_LPSC_ICSS 21 400fba27b6SVitaly Andrianov #define KS2_LPSC_DSS 23 410fba27b6SVitaly Andrianov #define KS2_LPSC_PCIE 24 420fba27b6SVitaly Andrianov #define KS2_LPSC_USB_0 25 430fba27b6SVitaly Andrianov #define KS2_LPSC_USB KS2_LPSC_USB_0 440fba27b6SVitaly Andrianov #define KS2_LPSC_USB_1 26 450fba27b6SVitaly Andrianov #define KS2_LPSC_DDR3 27 460fba27b6SVitaly Andrianov #define KS2_LPSC_SPARE0_LPSC0 28 470fba27b6SVitaly Andrianov #define KS2_LPSC_SPARE0_LPSC1 29 480fba27b6SVitaly Andrianov #define KS2_LPSC_SPARE1_LPSC0 30 490fba27b6SVitaly Andrianov #define KS2_LPSC_SPARE1_LPSC1 31 500fba27b6SVitaly Andrianov 510fba27b6SVitaly Andrianov #define KS2_LPSC_CPGMAC KS2_LPSC_NSS 520fba27b6SVitaly Andrianov #define KS2_LPSC_CRYPTO KS2_LPSC_SA 530fba27b6SVitaly Andrianov 5411d8222aSVitaly Andrianov /* SGMII SerDes */ 5511d8222aSVitaly Andrianov #define KS2_LANES_PER_SGMII_SERDES 4 5611d8222aSVitaly Andrianov 5711d8222aSVitaly Andrianov /* NETCP pktdma */ 5811d8222aSVitaly Andrianov #define KS2_NETCP_PDMA_CTRL_BASE 0x04010000 5911d8222aSVitaly Andrianov #define KS2_NETCP_PDMA_TX_BASE 0x04011000 6011d8222aSVitaly Andrianov #define KS2_NETCP_PDMA_TX_CH_NUM 21 6111d8222aSVitaly Andrianov #define KS2_NETCP_PDMA_RX_BASE 0x04012000 6211d8222aSVitaly Andrianov #define KS2_NETCP_PDMA_RX_CH_NUM 32 6311d8222aSVitaly Andrianov #define KS2_NETCP_PDMA_SCHED_BASE 0x04010100 6411d8222aSVitaly Andrianov #define KS2_NETCP_PDMA_RX_FLOW_BASE 0x04013000 6511d8222aSVitaly Andrianov #define KS2_NETCP_PDMA_RX_FLOW_NUM 32 6611d8222aSVitaly Andrianov #define KS2_NETCP_PDMA_TX_SND_QUEUE 5 6711d8222aSVitaly Andrianov 6811d8222aSVitaly Andrianov /* NETCP */ 6911d8222aSVitaly Andrianov #define KS2_NETCP_BASE 0x04000000 7011d8222aSVitaly Andrianov 7111d8222aSVitaly Andrianov #define K2G_GPIO0_BASE 0X02603000 7211d8222aSVitaly Andrianov #define K2G_GPIO1_BASE 0X0260a000 7311d8222aSVitaly Andrianov #define K2G_GPIO1_BANK2_BASE K2G_GPIO1_BASE + 0x38 7411d8222aSVitaly Andrianov #define K2G_GPIO_DIR_OFFSET 0x0 7511d8222aSVitaly Andrianov #define K2G_GPIO_SETDATA_OFFSET 0x8 7611d8222aSVitaly Andrianov 770fba27b6SVitaly Andrianov #endif /* __ASM_ARCH_HARDWARE_K2G_H */ 78