1*dc7de222SMasahiro Yamada /* 2*dc7de222SMasahiro Yamada * K2E: SoC definitions 3*dc7de222SMasahiro Yamada * 4*dc7de222SMasahiro Yamada * (C) Copyright 2012-2014 5*dc7de222SMasahiro Yamada * Texas Instruments Incorporated, <www.ti.com> 6*dc7de222SMasahiro Yamada * 7*dc7de222SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 8*dc7de222SMasahiro Yamada */ 9*dc7de222SMasahiro Yamada 10*dc7de222SMasahiro Yamada #ifndef __ASM_ARCH_HARDWARE_K2E_H 11*dc7de222SMasahiro Yamada #define __ASM_ARCH_HARDWARE_K2E_H 12*dc7de222SMasahiro Yamada 13*dc7de222SMasahiro Yamada /* PA SS Registers */ 14*dc7de222SMasahiro Yamada #define KS2_PASS_BASE 0x24000000 15*dc7de222SMasahiro Yamada 16*dc7de222SMasahiro Yamada /* Power and Sleep Controller (PSC) Domains */ 17*dc7de222SMasahiro Yamada #define KS2_LPSC_MOD_RST 0 18*dc7de222SMasahiro Yamada #define KS2_LPSC_USB_1 1 19*dc7de222SMasahiro Yamada #define KS2_LPSC_USB 2 20*dc7de222SMasahiro Yamada #define KS2_LPSC_EMIF25_SPI 3 21*dc7de222SMasahiro Yamada #define KS2_LPSC_TSIP 4 22*dc7de222SMasahiro Yamada #define KS2_LPSC_DEBUGSS_TRC 5 23*dc7de222SMasahiro Yamada #define KS2_LPSC_TETB_TRC 6 24*dc7de222SMasahiro Yamada #define KS2_LPSC_PKTPROC 7 25*dc7de222SMasahiro Yamada #define KS2_LPSC_PA KS2_LPSC_PKTPROC 26*dc7de222SMasahiro Yamada #define KS2_LPSC_SGMII 8 27*dc7de222SMasahiro Yamada #define KS2_LPSC_CPGMAC KS2_LPSC_SGMII 28*dc7de222SMasahiro Yamada #define KS2_LPSC_CRYPTO 9 29*dc7de222SMasahiro Yamada #define KS2_LPSC_PCIE 10 30*dc7de222SMasahiro Yamada #define KS2_LPSC_VUSR0 12 31*dc7de222SMasahiro Yamada #define KS2_LPSC_CHIP_SRSS 13 32*dc7de222SMasahiro Yamada #define KS2_LPSC_MSMC 14 33*dc7de222SMasahiro Yamada #define KS2_LPSC_EMIF4F_DDR3 23 34*dc7de222SMasahiro Yamada #define KS2_LPSC_PCIE_1 27 35*dc7de222SMasahiro Yamada #define KS2_LPSC_XGE 50 36*dc7de222SMasahiro Yamada 37*dc7de222SMasahiro Yamada /* MSMC */ 38*dc7de222SMasahiro Yamada #define KS2_MSMC_SEGMENT_PCIE1 13 39*dc7de222SMasahiro Yamada 40*dc7de222SMasahiro Yamada /* Chip Interrupt Controller */ 41*dc7de222SMasahiro Yamada #define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */ 42*dc7de222SMasahiro Yamada #define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */ 43*dc7de222SMasahiro Yamada 44*dc7de222SMasahiro Yamada /* SGMII SerDes */ 45*dc7de222SMasahiro Yamada #define KS2_SGMII_SERDES2_BASE 0x02324000 46*dc7de222SMasahiro Yamada #define KS2_LANES_PER_SGMII_SERDES 4 47*dc7de222SMasahiro Yamada 48*dc7de222SMasahiro Yamada /* Number of DSP cores */ 49*dc7de222SMasahiro Yamada #define KS2_NUM_DSPS 1 50*dc7de222SMasahiro Yamada 51*dc7de222SMasahiro Yamada /* NETCP pktdma */ 52*dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_CTRL_BASE 0x24186000 53*dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_TX_BASE 0x24187000 54*dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_TX_CH_NUM 21 55*dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_RX_BASE 0x24188000 56*dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_RX_CH_NUM 91 57*dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_SCHED_BASE 0x24186100 58*dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_RX_FLOW_BASE 0x24189000 59*dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_RX_FLOW_NUM 96 60*dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_TX_SND_QUEUE 896 61*dc7de222SMasahiro Yamada 62*dc7de222SMasahiro Yamada /* NETCP */ 63*dc7de222SMasahiro Yamada #define KS2_NETCP_BASE 0x24000000 64*dc7de222SMasahiro Yamada 65*dc7de222SMasahiro Yamada #endif 66