1 /* 2 * keystone2: common clock header file 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __ASM_ARCH_CLOCK_H 11 #define __ASM_ARCH_CLOCK_H 12 13 #ifndef __ASSEMBLY__ 14 15 #ifdef CONFIG_SOC_K2HK 16 #include <asm/arch/clock-k2hk.h> 17 #endif 18 19 #ifdef CONFIG_SOC_K2E 20 #include <asm/arch/clock-k2e.h> 21 #endif 22 23 #ifdef CONFIG_SOC_K2L 24 #include <asm/arch/clock-k2l.h> 25 #endif 26 27 #ifdef CONFIG_SOC_K2G 28 #include <asm/arch/clock-k2g.h> 29 #endif 30 31 #define CORE_PLL MAIN_PLL 32 #define DDR3_PLL DDR3A_PLL 33 #define NSS_PLL PASS_PLL 34 35 #define CLK_LIST(CLK)\ 36 CLK(0, core_pll_clk)\ 37 CLK(1, pass_pll_clk)\ 38 CLK(2, tetris_pll_clk)\ 39 CLK(3, ddr3a_pll_clk)\ 40 CLK(4, ddr3b_pll_clk)\ 41 CLK(5, sys_clk0_clk)\ 42 CLK(6, sys_clk0_1_clk)\ 43 CLK(7, sys_clk0_2_clk)\ 44 CLK(8, sys_clk0_3_clk)\ 45 CLK(9, sys_clk0_4_clk)\ 46 CLK(10, sys_clk0_6_clk)\ 47 CLK(11, sys_clk0_8_clk)\ 48 CLK(12, sys_clk0_12_clk)\ 49 CLK(13, sys_clk0_24_clk)\ 50 CLK(14, sys_clk1_clk)\ 51 CLK(15, sys_clk1_3_clk)\ 52 CLK(16, sys_clk1_4_clk)\ 53 CLK(17, sys_clk1_6_clk)\ 54 CLK(18, sys_clk1_12_clk)\ 55 CLK(19, sys_clk2_clk)\ 56 CLK(20, sys_clk3_clk) 57 58 #include <asm/types.h> 59 60 #define GENERATE_ENUM(NUM, ENUM) ENUM = NUM, 61 #define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n" 62 #define CLOCK_INDEXES_LIST CLK_LIST(GENERATE_INDX_STR) 63 64 enum { 65 SPD800, 66 SPD850, 67 SPD1000, 68 SPD1200, 69 SPD1250, 70 SPD1350, 71 SPD1400, 72 SPD1500, 73 NUM_SPDS, 74 }; 75 76 /* PLL identifiers */ 77 enum { 78 MAIN_PLL, 79 TETRIS_PLL, 80 PASS_PLL, 81 DDR3A_PLL, 82 DDR3B_PLL, 83 UART_PLL, 84 MAX_PLL_COUNT, 85 }; 86 87 enum ext_clk_e { 88 sys_clk, 89 alt_core_clk, 90 pa_clk, 91 tetris_clk, 92 ddr3a_clk, 93 ddr3b_clk, 94 ext_clk_count /* number of external clocks */ 95 }; 96 97 enum clk_e { 98 CLK_LIST(GENERATE_ENUM) 99 }; 100 101 struct keystone_pll_regs { 102 u32 reg0; 103 u32 reg1; 104 }; 105 106 /* PLL configuration data */ 107 struct pll_init_data { 108 int pll; 109 int pll_m; /* PLL Multiplier */ 110 int pll_d; /* PLL divider */ 111 int pll_od; /* PLL output divider */ 112 }; 113 114 extern unsigned int external_clk[ext_clk_count]; 115 extern const struct keystone_pll_regs keystone_pll_regs[]; 116 extern s16 divn_val[]; 117 extern int speeds[]; 118 119 void init_plls(void); 120 void init_pll(const struct pll_init_data *data); 121 struct pll_init_data *get_pll_init_data(int pll); 122 unsigned long clk_get_rate(unsigned int clk); 123 unsigned long clk_round_rate(unsigned int clk, unsigned long hz); 124 int clk_set_rate(unsigned int clk, unsigned long hz); 125 int get_max_dev_speed(void); 126 int get_max_arm_speed(void); 127 void pll_pa_clk_sel(void); 128 129 #endif 130 #endif 131