1 /* 2 * keystone2: common clock header file 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __ASM_ARCH_CLOCK_H 11 #define __ASM_ARCH_CLOCK_H 12 13 #ifndef __ASSEMBLY__ 14 15 #ifdef CONFIG_SOC_K2HK 16 #include <asm/arch/clock-k2hk.h> 17 #endif 18 19 #ifdef CONFIG_SOC_K2E 20 #include <asm/arch/clock-k2e.h> 21 #endif 22 23 #ifdef CONFIG_SOC_K2L 24 #include <asm/arch/clock-k2l.h> 25 #endif 26 27 #define CORE_PLL MAIN_PLL 28 #define DDR3_PLL DDR3A_PLL 29 30 #include <asm/types.h> 31 32 #define GENERATE_ENUM(NUM, ENUM) ENUM = NUM, 33 #define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n" 34 #define CLOCK_INDEXES_LIST CLK_LIST(GENERATE_INDX_STR) 35 36 enum { 37 SPD800, 38 SPD850, 39 SPD1000, 40 SPD1200, 41 SPD1250, 42 SPD1350, 43 SPD1400, 44 SPD1500, 45 NUM_SPDS, 46 }; 47 48 /* PLL identifiers */ 49 enum { 50 MAIN_PLL, 51 TETRIS_PLL, 52 PASS_PLL, 53 DDR3A_PLL, 54 DDR3B_PLL, 55 MAX_PLL_COUNT, 56 }; 57 58 enum ext_clk_e { 59 sys_clk, 60 alt_core_clk, 61 pa_clk, 62 tetris_clk, 63 ddr3a_clk, 64 ddr3b_clk, 65 ext_clk_count /* number of external clocks */ 66 }; 67 68 enum clk_e { 69 CLK_LIST(GENERATE_ENUM) 70 }; 71 72 struct keystone_pll_regs { 73 u32 reg0; 74 u32 reg1; 75 }; 76 77 /* PLL configuration data */ 78 struct pll_init_data { 79 int pll; 80 int pll_m; /* PLL Multiplier */ 81 int pll_d; /* PLL divider */ 82 int pll_od; /* PLL output divider */ 83 }; 84 85 extern unsigned int external_clk[ext_clk_count]; 86 extern const struct keystone_pll_regs keystone_pll_regs[]; 87 extern s16 divn_val[]; 88 extern int speeds[]; 89 90 void init_plls(void); 91 void init_pll(const struct pll_init_data *data); 92 struct pll_init_data *get_pll_init_data(int pll); 93 unsigned long clk_get_rate(unsigned int clk); 94 unsigned long clk_round_rate(unsigned int clk, unsigned long hz); 95 int clk_set_rate(unsigned int clk, unsigned long hz); 96 int get_max_dev_speed(void); 97 int get_max_arm_speed(void); 98 99 #endif 100 #endif 101