1dc7de222SMasahiro Yamada /* 2dc7de222SMasahiro Yamada * keystone2: common clock header file 3dc7de222SMasahiro Yamada * 4dc7de222SMasahiro Yamada * (C) Copyright 2012-2014 5dc7de222SMasahiro Yamada * Texas Instruments Incorporated, <www.ti.com> 6dc7de222SMasahiro Yamada * 7dc7de222SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 8dc7de222SMasahiro Yamada */ 9dc7de222SMasahiro Yamada 10dc7de222SMasahiro Yamada #ifndef __ASM_ARCH_CLOCK_H 11dc7de222SMasahiro Yamada #define __ASM_ARCH_CLOCK_H 12dc7de222SMasahiro Yamada 13dc7de222SMasahiro Yamada #ifndef __ASSEMBLY__ 14dc7de222SMasahiro Yamada 15dc7de222SMasahiro Yamada #ifdef CONFIG_SOC_K2HK 16dc7de222SMasahiro Yamada #include <asm/arch/clock-k2hk.h> 17dc7de222SMasahiro Yamada #endif 18dc7de222SMasahiro Yamada 19dc7de222SMasahiro Yamada #ifdef CONFIG_SOC_K2E 20dc7de222SMasahiro Yamada #include <asm/arch/clock-k2e.h> 21dc7de222SMasahiro Yamada #endif 22dc7de222SMasahiro Yamada 23dc7de222SMasahiro Yamada #ifdef CONFIG_SOC_K2L 24dc7de222SMasahiro Yamada #include <asm/arch/clock-k2l.h> 25dc7de222SMasahiro Yamada #endif 26dc7de222SMasahiro Yamada 2774af583eSLokesh Vutla #define CORE_PLL MAIN_PLL 2874af583eSLokesh Vutla #define DDR3_PLL DDR3A_PLL 29dc7de222SMasahiro Yamada 30dc7de222SMasahiro Yamada #include <asm/types.h> 31dc7de222SMasahiro Yamada 32dc7de222SMasahiro Yamada #define GENERATE_ENUM(NUM, ENUM) ENUM = NUM, 33dc7de222SMasahiro Yamada #define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n" 34dc7de222SMasahiro Yamada #define CLOCK_INDEXES_LIST CLK_LIST(GENERATE_INDX_STR) 35dc7de222SMasahiro Yamada 367b50e159SLokesh Vutla enum { 377b50e159SLokesh Vutla SPD800, 387b50e159SLokesh Vutla SPD850, 397b50e159SLokesh Vutla SPD1000, 407b50e159SLokesh Vutla SPD1200, 417b50e159SLokesh Vutla SPD1250, 427b50e159SLokesh Vutla SPD1350, 437b50e159SLokesh Vutla SPD1400, 447b50e159SLokesh Vutla SPD1500, 457b50e159SLokesh Vutla NUM_SPDS, 467b50e159SLokesh Vutla }; 477b50e159SLokesh Vutla 4874af583eSLokesh Vutla /* PLL identifiers */ 4974af583eSLokesh Vutla enum { 5074af583eSLokesh Vutla MAIN_PLL, 5174af583eSLokesh Vutla TETRIS_PLL, 5274af583eSLokesh Vutla PASS_PLL, 5374af583eSLokesh Vutla DDR3A_PLL, 5474af583eSLokesh Vutla DDR3B_PLL, 5574af583eSLokesh Vutla MAX_PLL_COUNT, 5674af583eSLokesh Vutla }; 5774af583eSLokesh Vutla 58dc7de222SMasahiro Yamada enum clk_e { 59dc7de222SMasahiro Yamada CLK_LIST(GENERATE_ENUM) 60dc7de222SMasahiro Yamada }; 61dc7de222SMasahiro Yamada 62dc7de222SMasahiro Yamada struct keystone_pll_regs { 63dc7de222SMasahiro Yamada u32 reg0; 64dc7de222SMasahiro Yamada u32 reg1; 65dc7de222SMasahiro Yamada }; 66dc7de222SMasahiro Yamada 67dc7de222SMasahiro Yamada /* PLL configuration data */ 68dc7de222SMasahiro Yamada struct pll_init_data { 69dc7de222SMasahiro Yamada int pll; 70dc7de222SMasahiro Yamada int pll_m; /* PLL Multiplier */ 71dc7de222SMasahiro Yamada int pll_d; /* PLL divider */ 72dc7de222SMasahiro Yamada int pll_od; /* PLL output divider */ 73dc7de222SMasahiro Yamada }; 74dc7de222SMasahiro Yamada 75dc7de222SMasahiro Yamada extern const struct keystone_pll_regs keystone_pll_regs[]; 76c321a236SLokesh Vutla extern s16 divn_val[]; 777b50e159SLokesh Vutla extern int speeds[]; 78dc7de222SMasahiro Yamada 79*94069301SLokesh Vutla void init_plls(void); 80dc7de222SMasahiro Yamada void init_pll(const struct pll_init_data *data); 81*94069301SLokesh Vutla struct pll_init_data *get_pll_init_data(int pll); 82dc7de222SMasahiro Yamada unsigned long clk_get_rate(unsigned int clk); 83dc7de222SMasahiro Yamada unsigned long clk_round_rate(unsigned int clk, unsigned long hz); 84dc7de222SMasahiro Yamada int clk_set_rate(unsigned int clk, unsigned long hz); 85dc7de222SMasahiro Yamada int get_max_dev_speed(void); 86dc7de222SMasahiro Yamada int get_max_arm_speed(void); 87dc7de222SMasahiro Yamada 88dc7de222SMasahiro Yamada #endif 89dc7de222SMasahiro Yamada #endif 90