1 /* 2 * K2HK: Clock management APIs 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __ASM_ARCH_CLOCK_K2HK_H 11 #define __ASM_ARCH_CLOCK_K2HK_H 12 13 enum ext_clk_e { 14 sys_clk, 15 alt_core_clk, 16 pa_clk, 17 tetris_clk, 18 ddr3a_clk, 19 ddr3b_clk, 20 mcm_clk, 21 pcie_clk, 22 sgmii_srio_clk, 23 xgmii_clk, 24 usb_clk, 25 rp1_clk, 26 ext_clk_count /* number of external clocks */ 27 }; 28 29 extern unsigned int external_clk[ext_clk_count]; 30 31 #define CLK_LIST(CLK)\ 32 CLK(0, core_pll_clk)\ 33 CLK(1, pass_pll_clk)\ 34 CLK(2, tetris_pll_clk)\ 35 CLK(3, ddr3a_pll_clk)\ 36 CLK(4, ddr3b_pll_clk)\ 37 CLK(5, sys_clk0_clk)\ 38 CLK(6, sys_clk0_1_clk)\ 39 CLK(7, sys_clk0_2_clk)\ 40 CLK(8, sys_clk0_3_clk)\ 41 CLK(9, sys_clk0_4_clk)\ 42 CLK(10, sys_clk0_6_clk)\ 43 CLK(11, sys_clk0_8_clk)\ 44 CLK(12, sys_clk0_12_clk)\ 45 CLK(13, sys_clk0_24_clk)\ 46 CLK(14, sys_clk1_clk)\ 47 CLK(15, sys_clk1_3_clk)\ 48 CLK(16, sys_clk1_4_clk)\ 49 CLK(17, sys_clk1_6_clk)\ 50 CLK(18, sys_clk1_12_clk)\ 51 CLK(19, sys_clk2_clk)\ 52 CLK(20, sys_clk3_clk) 53 54 #define PLLSET_CMD_LIST "<pa|arm|ddr3a|ddr3b>" 55 56 #define KS2_CLK1_6 sys_clk0_6_clk 57 58 /* PLL identifiers */ 59 enum pll_type_e { 60 CORE_PLL, 61 PASS_PLL, 62 TETRIS_PLL, 63 DDR3A_PLL, 64 DDR3B_PLL, 65 }; 66 67 #define CORE_PLL_799 {CORE_PLL, 13, 1, 2} 68 #define CORE_PLL_983 {CORE_PLL, 16, 1, 2} 69 #define CORE_PLL_999 {CORE_PLL, 122, 15, 1} 70 #define CORE_PLL_1167 {CORE_PLL, 19, 1, 2} 71 #define CORE_PLL_1228 {CORE_PLL, 20, 1, 2} 72 #define CORE_PLL_1200 {CORE_PLL, 625, 32, 2} 73 #define PASS_PLL_1228 {PASS_PLL, 20, 1, 2} 74 #define PASS_PLL_983 {PASS_PLL, 16, 1, 2} 75 #define PASS_PLL_1050 {PASS_PLL, 205, 12, 2} 76 #define TETRIS_PLL_500 {TETRIS_PLL, 8, 1, 2} 77 #define TETRIS_PLL_750 {TETRIS_PLL, 12, 1, 2} 78 #define TETRIS_PLL_800 {TETRIS_PLL, 32, 5, 1} 79 #define TETRIS_PLL_687 {TETRIS_PLL, 11, 1, 2} 80 #define TETRIS_PLL_625 {TETRIS_PLL, 10, 1, 2} 81 #define TETRIS_PLL_812 {TETRIS_PLL, 13, 1, 2} 82 #define TETRIS_PLL_875 {TETRIS_PLL, 14, 1, 2} 83 #define TETRIS_PLL_1000 {TETRIS_PLL, 40, 5, 1} 84 #define TETRIS_PLL_1188 {TETRIS_PLL, 19, 2, 1} 85 #define TETRIS_PLL_1200 {TETRIS_PLL, 48, 5, 1} 86 #define TETRIS_PLL_1350 {TETRIS_PLL, 54, 5, 1} 87 #define TETRIS_PLL_1375 {TETRIS_PLL, 22, 2, 1} 88 #define TETRIS_PLL_1400 {TETRIS_PLL, 56, 5, 1} 89 #define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2} 90 #define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4} 91 #define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2} 92 #define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6} 93 94 /* k2h DEV supports 800, 1000, 1200 MHz */ 95 #define DEV_SUPPORTED_SPEEDS 0x383 96 /* k2h ARM supportd 800, 1000, 1200, 1350, 1400 MHz */ 97 #define ARM_SUPPORTED_SPEEDS 0x3EF 98 99 #endif 100