1 /* 2 * K2E: Clock management APIs 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __ASM_ARCH_CLOCK_K2E_H 11 #define __ASM_ARCH_CLOCK_K2E_H 12 13 enum ext_clk_e { 14 sys_clk, 15 alt_core_clk, 16 pa_clk, 17 ddr3_clk, 18 mcm_clk, 19 pcie_clk, 20 sgmii_clk, 21 xgmii_clk, 22 usb_clk, 23 ext_clk_count /* number of external clocks */ 24 }; 25 26 extern unsigned int external_clk[ext_clk_count]; 27 28 #define CLK_LIST(CLK)\ 29 CLK(0, core_pll_clk)\ 30 CLK(1, pass_pll_clk)\ 31 CLK(2, ddr3_pll_clk)\ 32 CLK(3, sys_clk0_clk)\ 33 CLK(4, sys_clk0_1_clk)\ 34 CLK(5, sys_clk0_2_clk)\ 35 CLK(6, sys_clk0_3_clk)\ 36 CLK(7, sys_clk0_4_clk)\ 37 CLK(8, sys_clk0_6_clk)\ 38 CLK(9, sys_clk0_8_clk)\ 39 CLK(10, sys_clk0_12_clk)\ 40 CLK(11, sys_clk0_24_clk)\ 41 CLK(12, sys_clk1_clk)\ 42 CLK(13, sys_clk1_3_clk)\ 43 CLK(14, sys_clk1_4_clk)\ 44 CLK(15, sys_clk1_6_clk)\ 45 CLK(16, sys_clk1_12_clk)\ 46 CLK(17, sys_clk2_clk)\ 47 CLK(18, sys_clk3_clk) 48 49 #define PLLSET_CMD_LIST "<pa|ddr3>" 50 51 #define KS2_CLK1_6 sys_clk0_6_clk 52 53 /* PLL identifiers */ 54 enum pll_type_e { 55 CORE_PLL, 56 PASS_PLL, 57 DDR3_PLL, 58 TETRIS_PLL, 59 }; 60 61 #define CORE_PLL_800 {CORE_PLL, 16, 1, 2} 62 #define CORE_PLL_850 {CORE_PLL, 17, 1, 2} 63 #define CORE_PLL_1000 {CORE_PLL, 20, 1, 2} 64 #define CORE_PLL_1200 {CORE_PLL, 24, 1, 2} 65 #define PASS_PLL_1000 {PASS_PLL, 20, 1, 2} 66 #define CORE_PLL_1250 {CORE_PLL, 25, 1, 2} 67 #define CORE_PLL_1350 {CORE_PLL, 27, 1, 2} 68 #define CORE_PLL_1400 {CORE_PLL, 28, 1, 2} 69 #define CORE_PLL_1500 {CORE_PLL, 30, 1, 2} 70 #define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2} 71 #define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4} 72 #define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} 73 #define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6} 74 75 /* k2e DEV supports 800, 850, 1000, 1250, 1350, 1400, 1500 MHz */ 76 #define DEV_SUPPORTED_SPEEDS 0xFFF 77 #define ARM_SUPPORTED_SPEEDS 0 78 79 #endif 80