1 /* 2 * K2E: Clock management APIs 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __ASM_ARCH_CLOCK_K2E_H 11 #define __ASM_ARCH_CLOCK_K2E_H 12 13 #define CLK_LIST(CLK)\ 14 CLK(0, core_pll_clk)\ 15 CLK(1, pass_pll_clk)\ 16 CLK(2, ddr3_pll_clk)\ 17 CLK(3, sys_clk0_clk)\ 18 CLK(4, sys_clk0_1_clk)\ 19 CLK(5, sys_clk0_2_clk)\ 20 CLK(6, sys_clk0_3_clk)\ 21 CLK(7, sys_clk0_4_clk)\ 22 CLK(8, sys_clk0_6_clk)\ 23 CLK(9, sys_clk0_8_clk)\ 24 CLK(10, sys_clk0_12_clk)\ 25 CLK(11, sys_clk0_24_clk)\ 26 CLK(12, sys_clk1_clk)\ 27 CLK(13, sys_clk1_3_clk)\ 28 CLK(14, sys_clk1_4_clk)\ 29 CLK(15, sys_clk1_6_clk)\ 30 CLK(16, sys_clk1_12_clk)\ 31 CLK(17, sys_clk2_clk)\ 32 CLK(18, sys_clk3_clk) 33 34 #define PLLSET_CMD_LIST "<pa|ddr3>" 35 36 #define KS2_CLK1_6 sys_clk0_6_clk 37 38 #define CORE_PLL_800 {CORE_PLL, 16, 1, 2} 39 #define CORE_PLL_850 {CORE_PLL, 17, 1, 2} 40 #define CORE_PLL_1000 {CORE_PLL, 20, 1, 2} 41 #define CORE_PLL_1200 {CORE_PLL, 24, 1, 2} 42 #define PASS_PLL_1000 {PASS_PLL, 20, 1, 2} 43 #define CORE_PLL_1250 {CORE_PLL, 25, 1, 2} 44 #define CORE_PLL_1350 {CORE_PLL, 27, 1, 2} 45 #define CORE_PLL_1400 {CORE_PLL, 28, 1, 2} 46 #define CORE_PLL_1500 {CORE_PLL, 30, 1, 2} 47 #define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2} 48 #define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4} 49 #define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} 50 #define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6} 51 52 /* k2e DEV supports 800, 850, 1000, 1250, 1350, 1400, 1500 MHz */ 53 #define DEV_SUPPORTED_SPEEDS 0xFFF 54 #define ARM_SUPPORTED_SPEEDS 0 55 56 #endif 57