1*dc7de222SMasahiro Yamada /* 2*dc7de222SMasahiro Yamada * K2E: Clock management APIs 3*dc7de222SMasahiro Yamada * 4*dc7de222SMasahiro Yamada * (C) Copyright 2012-2014 5*dc7de222SMasahiro Yamada * Texas Instruments Incorporated, <www.ti.com> 6*dc7de222SMasahiro Yamada * 7*dc7de222SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 8*dc7de222SMasahiro Yamada */ 9*dc7de222SMasahiro Yamada 10*dc7de222SMasahiro Yamada #ifndef __ASM_ARCH_CLOCK_K2E_H 11*dc7de222SMasahiro Yamada #define __ASM_ARCH_CLOCK_K2E_H 12*dc7de222SMasahiro Yamada 13*dc7de222SMasahiro Yamada enum ext_clk_e { 14*dc7de222SMasahiro Yamada sys_clk, 15*dc7de222SMasahiro Yamada alt_core_clk, 16*dc7de222SMasahiro Yamada pa_clk, 17*dc7de222SMasahiro Yamada ddr3_clk, 18*dc7de222SMasahiro Yamada mcm_clk, 19*dc7de222SMasahiro Yamada pcie_clk, 20*dc7de222SMasahiro Yamada sgmii_clk, 21*dc7de222SMasahiro Yamada xgmii_clk, 22*dc7de222SMasahiro Yamada usb_clk, 23*dc7de222SMasahiro Yamada ext_clk_count /* number of external clocks */ 24*dc7de222SMasahiro Yamada }; 25*dc7de222SMasahiro Yamada 26*dc7de222SMasahiro Yamada extern unsigned int external_clk[ext_clk_count]; 27*dc7de222SMasahiro Yamada 28*dc7de222SMasahiro Yamada #define CLK_LIST(CLK)\ 29*dc7de222SMasahiro Yamada CLK(0, core_pll_clk)\ 30*dc7de222SMasahiro Yamada CLK(1, pass_pll_clk)\ 31*dc7de222SMasahiro Yamada CLK(2, ddr3_pll_clk)\ 32*dc7de222SMasahiro Yamada CLK(3, sys_clk0_clk)\ 33*dc7de222SMasahiro Yamada CLK(4, sys_clk0_1_clk)\ 34*dc7de222SMasahiro Yamada CLK(5, sys_clk0_2_clk)\ 35*dc7de222SMasahiro Yamada CLK(6, sys_clk0_3_clk)\ 36*dc7de222SMasahiro Yamada CLK(7, sys_clk0_4_clk)\ 37*dc7de222SMasahiro Yamada CLK(8, sys_clk0_6_clk)\ 38*dc7de222SMasahiro Yamada CLK(9, sys_clk0_8_clk)\ 39*dc7de222SMasahiro Yamada CLK(10, sys_clk0_12_clk)\ 40*dc7de222SMasahiro Yamada CLK(11, sys_clk0_24_clk)\ 41*dc7de222SMasahiro Yamada CLK(12, sys_clk1_clk)\ 42*dc7de222SMasahiro Yamada CLK(13, sys_clk1_3_clk)\ 43*dc7de222SMasahiro Yamada CLK(14, sys_clk1_4_clk)\ 44*dc7de222SMasahiro Yamada CLK(15, sys_clk1_6_clk)\ 45*dc7de222SMasahiro Yamada CLK(16, sys_clk1_12_clk)\ 46*dc7de222SMasahiro Yamada CLK(17, sys_clk2_clk)\ 47*dc7de222SMasahiro Yamada CLK(18, sys_clk3_clk) 48*dc7de222SMasahiro Yamada 49*dc7de222SMasahiro Yamada #define PLLSET_CMD_LIST "<pa|ddr3>" 50*dc7de222SMasahiro Yamada 51*dc7de222SMasahiro Yamada #define KS2_CLK1_6 sys_clk0_6_clk 52*dc7de222SMasahiro Yamada 53*dc7de222SMasahiro Yamada /* PLL identifiers */ 54*dc7de222SMasahiro Yamada enum pll_type_e { 55*dc7de222SMasahiro Yamada CORE_PLL, 56*dc7de222SMasahiro Yamada PASS_PLL, 57*dc7de222SMasahiro Yamada DDR3_PLL, 58*dc7de222SMasahiro Yamada }; 59*dc7de222SMasahiro Yamada 60*dc7de222SMasahiro Yamada enum { 61*dc7de222SMasahiro Yamada SPD800, 62*dc7de222SMasahiro Yamada SPD850, 63*dc7de222SMasahiro Yamada SPD1000, 64*dc7de222SMasahiro Yamada SPD1250, 65*dc7de222SMasahiro Yamada SPD1350, 66*dc7de222SMasahiro Yamada SPD1400, 67*dc7de222SMasahiro Yamada SPD1500, 68*dc7de222SMasahiro Yamada SPD_RSV 69*dc7de222SMasahiro Yamada }; 70*dc7de222SMasahiro Yamada 71*dc7de222SMasahiro Yamada #define CORE_PLL_800 {CORE_PLL, 16, 1, 2} 72*dc7de222SMasahiro Yamada #define CORE_PLL_850 {CORE_PLL, 17, 1, 2} 73*dc7de222SMasahiro Yamada #define CORE_PLL_1000 {CORE_PLL, 20, 1, 2} 74*dc7de222SMasahiro Yamada #define CORE_PLL_1200 {CORE_PLL, 24, 1, 2} 75*dc7de222SMasahiro Yamada #define PASS_PLL_1000 {PASS_PLL, 20, 1, 2} 76*dc7de222SMasahiro Yamada #define CORE_PLL_1250 {CORE_PLL, 25, 1, 2} 77*dc7de222SMasahiro Yamada #define CORE_PLL_1350 {CORE_PLL, 27, 1, 2} 78*dc7de222SMasahiro Yamada #define CORE_PLL_1400 {CORE_PLL, 28, 1, 2} 79*dc7de222SMasahiro Yamada #define CORE_PLL_1500 {CORE_PLL, 30, 1, 2} 80*dc7de222SMasahiro Yamada #define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2} 81*dc7de222SMasahiro Yamada #define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4} 82*dc7de222SMasahiro Yamada #define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} 83*dc7de222SMasahiro Yamada #define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6} 84*dc7de222SMasahiro Yamada 85*dc7de222SMasahiro Yamada #endif 86