1 /* 2 * Keystone2: pll initialization 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/clock_defs.h> 13 14 /* DEV and ARM speed definitions as specified in DEVSPEED register */ 15 int __weak speeds[DEVSPEED_NUMSPDS] = { 16 SPD1000, 17 SPD1200, 18 SPD1350, 19 SPD1400, 20 SPD1500, 21 SPD1400, 22 SPD1350, 23 SPD1200, 24 SPD1000, 25 SPD800, 26 }; 27 28 static void wait_for_completion(const struct pll_init_data *data) 29 { 30 int i; 31 for (i = 0; i < 100; i++) { 32 sdelay(450); 33 if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK)) 34 break; 35 } 36 } 37 38 static inline void bypass_main_pll(const struct pll_init_data *data) 39 { 40 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK | 41 PLLCTL_PLLEN_MASK); 42 43 /* 4 cycles of reference clock CLKIN*/ 44 sdelay(340); 45 } 46 47 static void configure_mult_div(const struct pll_init_data *data) 48 { 49 u32 pllm, plld, bwadj; 50 51 pllm = data->pll_m - 1; 52 plld = (data->pll_d - 1) & CFG_PLLCTL0_PLLD_MASK; 53 54 /* Program Multiplier */ 55 if (data->pll == MAIN_PLL) 56 pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK); 57 58 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, 59 CFG_PLLCTL0_PLLM_MASK, 60 pllm << CFG_PLLCTL0_PLLM_SHIFT); 61 62 /* Program BWADJ */ 63 bwadj = (data->pll_m - 1) >> 1; /* Divide pllm by 2 */ 64 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, 65 CFG_PLLCTL0_BWADJ_MASK, 66 (bwadj << CFG_PLLCTL0_BWADJ_SHIFT) & 67 CFG_PLLCTL0_BWADJ_MASK); 68 bwadj = bwadj >> CFG_PLLCTL0_BWADJ_BITS; 69 clrsetbits_le32(keystone_pll_regs[data->pll].reg1, 70 CFG_PLLCTL1_BWADJ_MASK, bwadj); 71 72 /* Program Divider */ 73 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, 74 CFG_PLLCTL0_PLLD_MASK, plld); 75 } 76 77 void configure_main_pll(const struct pll_init_data *data) 78 { 79 u32 tmp, pllod, i, alnctl_val = 0; 80 u32 *offset; 81 82 pllod = data->pll_od - 1; 83 84 /* 100 micro sec for stabilization */ 85 sdelay(210000); 86 87 tmp = pllctl_reg_read(data->pll, secctl); 88 89 /* Check for Bypass */ 90 if (tmp & SECCTL_BYPASS_MASK) { 91 setbits_le32(keystone_pll_regs[data->pll].reg1, 92 CFG_PLLCTL1_ENSAT_MASK); 93 94 bypass_main_pll(data); 95 96 /* Powerdown and powerup Main Pll */ 97 pllctl_reg_setbits(data->pll, secctl, SECCTL_BYPASS_MASK); 98 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK); 99 /* 5 micro sec */ 100 sdelay(21000); 101 102 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK); 103 } else { 104 bypass_main_pll(data); 105 } 106 107 configure_mult_div(data); 108 109 /* Program Output Divider */ 110 pllctl_reg_rmw(data->pll, secctl, SECCTL_OP_DIV_MASK, 111 ((pllod << SECCTL_OP_DIV_SHIFT) & SECCTL_OP_DIV_MASK)); 112 113 /* Program PLLDIVn */ 114 wait_for_completion(data); 115 for (i = 0; i < PLLDIV_MAX; i++) { 116 if (i < 3) 117 offset = pllctl_reg(data->pll, div1) + i; 118 else 119 offset = pllctl_reg(data->pll, div4) + (i - 3); 120 121 if (divn_val[i] != -1) { 122 __raw_writel(divn_val[i] | PLLDIV_ENABLE_MASK, offset); 123 alnctl_val |= BIT(i); 124 } 125 } 126 127 if (alnctl_val) { 128 pllctl_reg_setbits(data->pll, alnctl, alnctl_val); 129 /* 130 * Set GOSET bit in PLLCMD to initiate the GO operation 131 * to change the divide 132 */ 133 pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GOSTAT_MASK); 134 wait_for_completion(data); 135 } 136 137 /* Reset PLL */ 138 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST_MASK); 139 sdelay(21000); /* Wait for a minimum of 7 us*/ 140 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST_MASK); 141 sdelay(105000); /* Wait for PLL Lock time (min 50 us) */ 142 143 /* Enable PLL */ 144 pllctl_reg_clrbits(data->pll, secctl, SECCTL_BYPASS_MASK); 145 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN_MASK); 146 } 147 148 void configure_secondary_pll(const struct pll_init_data *data) 149 { 150 int pllod = data->pll_od - 1; 151 152 /* Enable Bypass mode */ 153 setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK); 154 setbits_le32(keystone_pll_regs[data->pll].reg0, 155 CFG_PLLCTL0_BYPASS_MASK); 156 157 /* Enable Glitch free bypass for ARM PLL */ 158 if (cpu_is_k2hk() && data->pll == TETRIS_PLL) 159 clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN); 160 161 configure_mult_div(data); 162 163 /* Program Output Divider */ 164 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, 165 CFG_PLLCTL0_CLKOD_MASK, 166 (pllod << CFG_PLLCTL0_CLKOD_SHIFT) & 167 CFG_PLLCTL0_CLKOD_MASK); 168 169 /* Reset PLL */ 170 setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK); 171 /* Wait for 5 micro seconds */ 172 sdelay(21000); 173 174 /* Select the Output of PASS PLL as input to PASS */ 175 if (data->pll == PASS_PLL) 176 setbits_le32(keystone_pll_regs[data->pll].reg1, 177 CFG_PLLCTL1_PAPLL_MASK); 178 179 /* Select the Output of ARM PLL as input to ARM */ 180 if (data->pll == TETRIS_PLL) 181 setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN); 182 183 clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK); 184 /* Wait for 500 * REFCLK cucles * (PLLD + 1) */ 185 sdelay(105000); 186 187 /* Switch to PLL mode */ 188 clrbits_le32(keystone_pll_regs[data->pll].reg0, 189 CFG_PLLCTL0_BYPASS_MASK); 190 } 191 192 void init_pll(const struct pll_init_data *data) 193 { 194 if (data->pll == MAIN_PLL) 195 configure_main_pll(data); 196 else 197 configure_secondary_pll(data); 198 199 /* 200 * This is required to provide a delay between multiple 201 * consequent PPL configurations 202 */ 203 sdelay(210000); 204 } 205 206 void init_plls(int num_pll, struct pll_init_data *config) 207 { 208 int i; 209 210 for (i = 0; i < num_pll; i++) 211 init_pll(&config[i]); 212 } 213 214 static int get_max_speed(u32 val, u32 speed_supported) 215 { 216 int speed; 217 218 /* Left most setbit gives the speed */ 219 for (speed = DEVSPEED_NUMSPDS; speed >= 0; speed--) { 220 if ((val & BIT(speed)) & speed_supported) 221 return speeds[speed]; 222 } 223 224 /* If no bit is set, use SPD800 */ 225 return SPD800; 226 } 227 228 static inline u32 read_efuse_bootrom(void) 229 { 230 if (cpu_is_k2hk() && (cpu_revision() <= 1)) 231 return __raw_readl(KS2_REV1_DEVSPEED); 232 else 233 return __raw_readl(KS2_EFUSE_BOOTROM); 234 } 235 236 int get_max_arm_speed(void) 237 { 238 u32 armspeed = read_efuse_bootrom(); 239 240 armspeed = (armspeed & DEVSPEED_ARMSPEED_MASK) >> 241 DEVSPEED_ARMSPEED_SHIFT; 242 243 return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS); 244 } 245 246 int get_max_dev_speed(void) 247 { 248 u32 devspeed = read_efuse_bootrom(); 249 250 devspeed = (devspeed & DEVSPEED_DEVSPEED_MASK) >> 251 DEVSPEED_DEVSPEED_SHIFT; 252 253 return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS); 254 } 255