1 /* 2 * Keystone2: pll initialization 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/clock_defs.h> 13 14 /* DEV and ARM speed definitions as specified in DEVSPEED register */ 15 int __weak speeds[DEVSPEED_NUMSPDS] = { 16 SPD1000, 17 SPD1200, 18 SPD1350, 19 SPD1400, 20 SPD1500, 21 SPD1400, 22 SPD1350, 23 SPD1200, 24 SPD1000, 25 SPD800, 26 }; 27 28 const struct keystone_pll_regs keystone_pll_regs[] = { 29 [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, 30 [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, 31 [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1}, 32 [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, 33 [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1}, 34 }; 35 36 static void wait_for_completion(const struct pll_init_data *data) 37 { 38 int i; 39 for (i = 0; i < 100; i++) { 40 sdelay(450); 41 if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK)) 42 break; 43 } 44 } 45 46 static inline void bypass_main_pll(const struct pll_init_data *data) 47 { 48 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK | 49 PLLCTL_PLLEN_MASK); 50 51 /* 4 cycles of reference clock CLKIN*/ 52 sdelay(340); 53 } 54 55 static void configure_mult_div(const struct pll_init_data *data) 56 { 57 u32 pllm, plld, bwadj; 58 59 pllm = data->pll_m - 1; 60 plld = (data->pll_d - 1) & CFG_PLLCTL0_PLLD_MASK; 61 62 /* Program Multiplier */ 63 if (data->pll == MAIN_PLL) 64 pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK); 65 66 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, 67 CFG_PLLCTL0_PLLM_MASK, 68 pllm << CFG_PLLCTL0_PLLM_SHIFT); 69 70 /* Program BWADJ */ 71 bwadj = (data->pll_m - 1) >> 1; /* Divide pllm by 2 */ 72 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, 73 CFG_PLLCTL0_BWADJ_MASK, 74 (bwadj << CFG_PLLCTL0_BWADJ_SHIFT) & 75 CFG_PLLCTL0_BWADJ_MASK); 76 bwadj = bwadj >> CFG_PLLCTL0_BWADJ_BITS; 77 clrsetbits_le32(keystone_pll_regs[data->pll].reg1, 78 CFG_PLLCTL1_BWADJ_MASK, bwadj); 79 80 /* Program Divider */ 81 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, 82 CFG_PLLCTL0_PLLD_MASK, plld); 83 } 84 85 void configure_main_pll(const struct pll_init_data *data) 86 { 87 u32 tmp, pllod, i, alnctl_val = 0; 88 u32 *offset; 89 90 pllod = data->pll_od - 1; 91 92 /* 100 micro sec for stabilization */ 93 sdelay(210000); 94 95 tmp = pllctl_reg_read(data->pll, secctl); 96 97 /* Check for Bypass */ 98 if (tmp & SECCTL_BYPASS_MASK) { 99 setbits_le32(keystone_pll_regs[data->pll].reg1, 100 CFG_PLLCTL1_ENSAT_MASK); 101 102 bypass_main_pll(data); 103 104 /* Powerdown and powerup Main Pll */ 105 pllctl_reg_setbits(data->pll, secctl, SECCTL_BYPASS_MASK); 106 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK); 107 /* 5 micro sec */ 108 sdelay(21000); 109 110 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK); 111 } else { 112 bypass_main_pll(data); 113 } 114 115 configure_mult_div(data); 116 117 /* Program Output Divider */ 118 pllctl_reg_rmw(data->pll, secctl, SECCTL_OP_DIV_MASK, 119 ((pllod << SECCTL_OP_DIV_SHIFT) & SECCTL_OP_DIV_MASK)); 120 121 /* Program PLLDIVn */ 122 wait_for_completion(data); 123 for (i = 0; i < PLLDIV_MAX; i++) { 124 if (i < 3) 125 offset = pllctl_reg(data->pll, div1) + i; 126 else 127 offset = pllctl_reg(data->pll, div4) + (i - 3); 128 129 if (divn_val[i] != -1) { 130 __raw_writel(divn_val[i] | PLLDIV_ENABLE_MASK, offset); 131 alnctl_val |= BIT(i); 132 } 133 } 134 135 if (alnctl_val) { 136 pllctl_reg_setbits(data->pll, alnctl, alnctl_val); 137 /* 138 * Set GOSET bit in PLLCMD to initiate the GO operation 139 * to change the divide 140 */ 141 pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GOSTAT_MASK); 142 wait_for_completion(data); 143 } 144 145 /* Reset PLL */ 146 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST_MASK); 147 sdelay(21000); /* Wait for a minimum of 7 us*/ 148 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST_MASK); 149 sdelay(105000); /* Wait for PLL Lock time (min 50 us) */ 150 151 /* Enable PLL */ 152 pllctl_reg_clrbits(data->pll, secctl, SECCTL_BYPASS_MASK); 153 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN_MASK); 154 } 155 156 void configure_secondary_pll(const struct pll_init_data *data) 157 { 158 int pllod = data->pll_od - 1; 159 160 /* Enable Bypass mode */ 161 setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK); 162 setbits_le32(keystone_pll_regs[data->pll].reg0, 163 CFG_PLLCTL0_BYPASS_MASK); 164 165 /* Enable Glitch free bypass for ARM PLL */ 166 if (cpu_is_k2hk() && data->pll == TETRIS_PLL) 167 clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN); 168 169 configure_mult_div(data); 170 171 /* Program Output Divider */ 172 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, 173 CFG_PLLCTL0_CLKOD_MASK, 174 (pllod << CFG_PLLCTL0_CLKOD_SHIFT) & 175 CFG_PLLCTL0_CLKOD_MASK); 176 177 /* Reset PLL */ 178 setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK); 179 /* Wait for 5 micro seconds */ 180 sdelay(21000); 181 182 /* Select the Output of PASS PLL as input to PASS */ 183 if (data->pll == PASS_PLL) 184 setbits_le32(keystone_pll_regs[data->pll].reg1, 185 CFG_PLLCTL1_PAPLL_MASK); 186 187 /* Select the Output of ARM PLL as input to ARM */ 188 if (data->pll == TETRIS_PLL) 189 setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN); 190 191 clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK); 192 /* Wait for 500 * REFCLK cucles * (PLLD + 1) */ 193 sdelay(105000); 194 195 /* Switch to PLL mode */ 196 clrbits_le32(keystone_pll_regs[data->pll].reg0, 197 CFG_PLLCTL0_BYPASS_MASK); 198 } 199 200 void init_pll(const struct pll_init_data *data) 201 { 202 if (data->pll == MAIN_PLL) 203 configure_main_pll(data); 204 else 205 configure_secondary_pll(data); 206 207 /* 208 * This is required to provide a delay between multiple 209 * consequent PPL configurations 210 */ 211 sdelay(210000); 212 } 213 214 void init_plls(int num_pll, struct pll_init_data *config) 215 { 216 int i; 217 218 for (i = 0; i < num_pll; i++) 219 init_pll(&config[i]); 220 } 221 222 static int get_max_speed(u32 val, u32 speed_supported) 223 { 224 int speed; 225 226 /* Left most setbit gives the speed */ 227 for (speed = DEVSPEED_NUMSPDS; speed >= 0; speed--) { 228 if ((val & BIT(speed)) & speed_supported) 229 return speeds[speed]; 230 } 231 232 /* If no bit is set, use SPD800 */ 233 return SPD800; 234 } 235 236 static inline u32 read_efuse_bootrom(void) 237 { 238 if (cpu_is_k2hk() && (cpu_revision() <= 1)) 239 return __raw_readl(KS2_REV1_DEVSPEED); 240 else 241 return __raw_readl(KS2_EFUSE_BOOTROM); 242 } 243 244 int get_max_arm_speed(void) 245 { 246 u32 armspeed = read_efuse_bootrom(); 247 248 armspeed = (armspeed & DEVSPEED_ARMSPEED_MASK) >> 249 DEVSPEED_ARMSPEED_SHIFT; 250 251 return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS); 252 } 253 254 int get_max_dev_speed(void) 255 { 256 u32 devspeed = read_efuse_bootrom(); 257 258 devspeed = (devspeed & DEVSPEED_DEVSPEED_MASK) >> 259 DEVSPEED_DEVSPEED_SHIFT; 260 261 return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS); 262 } 263