xref: /rk3399_rockchip-uboot/arch/arm/mach-imx/speed.c (revision 39632b4a01210e329333d787d828157dcd2c7328)
1*552a848eSStefano Babic /*
2*552a848eSStefano Babic  * (C) Copyright 2000-2003
3*552a848eSStefano Babic  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4*552a848eSStefano Babic  *
5*552a848eSStefano Babic  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6*552a848eSStefano Babic  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7*552a848eSStefano Babic  *
8*552a848eSStefano Babic  * SPDX-License-Identifier:	GPL-2.0+
9*552a848eSStefano Babic  */
10*552a848eSStefano Babic 
11*552a848eSStefano Babic #include <common.h>
12*552a848eSStefano Babic #include <asm/arch/imx-regs.h>
13*552a848eSStefano Babic #include <asm/arch/clock.h>
14*552a848eSStefano Babic 
15*552a848eSStefano Babic #ifdef CONFIG_FSL_ESDHC
16*552a848eSStefano Babic DECLARE_GLOBAL_DATA_PTR;
17*552a848eSStefano Babic #endif
18*552a848eSStefano Babic 
get_clocks(void)19*552a848eSStefano Babic int get_clocks(void)
20*552a848eSStefano Babic {
21*552a848eSStefano Babic #ifdef CONFIG_FSL_ESDHC
22*552a848eSStefano Babic #ifdef CONFIG_FSL_USDHC
23*552a848eSStefano Babic #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
24*552a848eSStefano Babic 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
25*552a848eSStefano Babic #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
26*552a848eSStefano Babic 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
27*552a848eSStefano Babic #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
28*552a848eSStefano Babic 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
29*552a848eSStefano Babic #else
30*552a848eSStefano Babic 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
31*552a848eSStefano Babic #endif
32*552a848eSStefano Babic #else
33*552a848eSStefano Babic #if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
34*552a848eSStefano Babic 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
35*552a848eSStefano Babic #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
36*552a848eSStefano Babic 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
37*552a848eSStefano Babic #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
38*552a848eSStefano Babic 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
39*552a848eSStefano Babic #else
40*552a848eSStefano Babic 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
41*552a848eSStefano Babic #endif
42*552a848eSStefano Babic #endif
43*552a848eSStefano Babic #endif
44*552a848eSStefano Babic 	return 0;
45*552a848eSStefano Babic }
46