1*552a848eSStefano Babic /* 2*552a848eSStefano Babic * Copyright 2011 Freescale Semiconductor, Inc. 3*552a848eSStefano Babic * 4*552a848eSStefano Babic * SPDX-License-Identifier: GPL-2.0+ 5*552a848eSStefano Babic */ 6*552a848eSStefano Babic 7*552a848eSStefano Babic #include <asm/mach-imx/iomux-v3.h> 8*552a848eSStefano Babic #include <asm/arch/iomux.h> 9*552a848eSStefano Babic #include <asm/io.h> 10*552a848eSStefano Babic #include <asm/arch/clock.h> 11*552a848eSStefano Babic #include <asm/arch/sys_proto.h> 12*552a848eSStefano Babic setup_sata(void)13*552a848eSStefano Babicint setup_sata(void) 14*552a848eSStefano Babic { 15*552a848eSStefano Babic struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 16*552a848eSStefano Babic int ret; 17*552a848eSStefano Babic 18*552a848eSStefano Babic if (!is_mx6dq() && !is_mx6dqp()) 19*552a848eSStefano Babic return 1; 20*552a848eSStefano Babic 21*552a848eSStefano Babic ret = enable_sata_clock(); 22*552a848eSStefano Babic if (ret) 23*552a848eSStefano Babic return ret; 24*552a848eSStefano Babic 25*552a848eSStefano Babic clrsetbits_le32(&iomuxc_regs->gpr[13], 26*552a848eSStefano Babic IOMUXC_GPR13_SATA_MASK, 27*552a848eSStefano Babic IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB 28*552a848eSStefano Babic |IOMUXC_GPR13_SATA_PHY_7_SATA2M 29*552a848eSStefano Babic |IOMUXC_GPR13_SATA_SPEED_3G 30*552a848eSStefano Babic |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) 31*552a848eSStefano Babic |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED 32*552a848eSStefano Babic |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 33*552a848eSStefano Babic |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB 34*552a848eSStefano Babic |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V 35*552a848eSStefano Babic |IOMUXC_GPR13_SATA_PHY_1_SLOW); 36*552a848eSStefano Babic 37*552a848eSStefano Babic return 0; 38*552a848eSStefano Babic } 39