1*552a848eSStefano Babic /*
2*552a848eSStefano Babic * Copyright (C) 2016 Freescale Semiconductor, Inc.
3*552a848eSStefano Babic *
4*552a848eSStefano Babic * SPDX-License-Identifier: GPL-2.0+
5*552a848eSStefano Babic */
6*552a848eSStefano Babic #include <common.h>
7*552a848eSStefano Babic #include <asm/io.h>
8*552a848eSStefano Babic #include <asm/arch/imx-regs.h>
9*552a848eSStefano Babic #include <asm/arch/iomux.h>
10*552a848eSStefano Babic
11*552a848eSStefano Babic static void *base = (void *)IOMUXC_BASE_ADDR;
12*552a848eSStefano Babic
13*552a848eSStefano Babic /*
14*552a848eSStefano Babic * iomuxc0 base address. In imx7ulp-pins.h,
15*552a848eSStefano Babic * the offsets of pins in iomuxc0 are from 0xD000,
16*552a848eSStefano Babic * so we set the base address to (0x4103D000 - 0xD000 = 0x41030000)
17*552a848eSStefano Babic */
18*552a848eSStefano Babic static void *base_mports = (void *)(AIPS0_BASE + 0x30000);
19*552a848eSStefano Babic
20*552a848eSStefano Babic /*
21*552a848eSStefano Babic * configures a single pad in the iomuxer
22*552a848eSStefano Babic */
mx7ulp_iomux_setup_pad(iomux_cfg_t pad)23*552a848eSStefano Babic void mx7ulp_iomux_setup_pad(iomux_cfg_t pad)
24*552a848eSStefano Babic {
25*552a848eSStefano Babic u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
26*552a848eSStefano Babic u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
27*552a848eSStefano Babic u32 sel_input_ofs =
28*552a848eSStefano Babic (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
29*552a848eSStefano Babic u32 sel_input =
30*552a848eSStefano Babic (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
31*552a848eSStefano Babic u32 pad_ctrl_ofs = mux_ctrl_ofs;
32*552a848eSStefano Babic u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
33*552a848eSStefano Babic
34*552a848eSStefano Babic debug("[PAD CFG] = 0x%16llX \r\n\tmux_ctl = 0x%X(0x%X) sel_input = 0x%X(0x%X) pad_ctrl = 0x%X(0x%X)\r\n",
35*552a848eSStefano Babic pad, mux_ctrl_ofs, mux_mode, sel_input_ofs, sel_input,
36*552a848eSStefano Babic pad_ctrl_ofs, pad_ctrl);
37*552a848eSStefano Babic
38*552a848eSStefano Babic if (mux_mode & IOMUX_CONFIG_MPORTS) {
39*552a848eSStefano Babic mux_mode &= ~IOMUX_CONFIG_MPORTS;
40*552a848eSStefano Babic base = base_mports;
41*552a848eSStefano Babic } else {
42*552a848eSStefano Babic base = (void *)IOMUXC_BASE_ADDR;
43*552a848eSStefano Babic }
44*552a848eSStefano Babic
45*552a848eSStefano Babic __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
46*552a848eSStefano Babic IOMUXC_PCR_MUX_ALT_MASK), base + mux_ctrl_ofs);
47*552a848eSStefano Babic
48*552a848eSStefano Babic if (sel_input_ofs)
49*552a848eSStefano Babic __raw_writel((sel_input << IOMUXC_PSMI_IMUX_ALT_SHIFT),
50*552a848eSStefano Babic base + sel_input_ofs);
51*552a848eSStefano Babic
52*552a848eSStefano Babic if (!(pad_ctrl & NO_PAD_CTRL))
53*552a848eSStefano Babic __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
54*552a848eSStefano Babic IOMUXC_PCR_MUX_ALT_MASK) |
55*552a848eSStefano Babic (pad_ctrl & (~IOMUXC_PCR_MUX_ALT_MASK)),
56*552a848eSStefano Babic base + pad_ctrl_ofs);
57*552a848eSStefano Babic }
58*552a848eSStefano Babic
59*552a848eSStefano Babic /* configures a list of pads within declared with IOMUX_PADS macro */
mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const * pad_list,unsigned count)60*552a848eSStefano Babic void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list,
61*552a848eSStefano Babic unsigned count)
62*552a848eSStefano Babic {
63*552a848eSStefano Babic iomux_cfg_t const *p = pad_list;
64*552a848eSStefano Babic int i;
65*552a848eSStefano Babic
66*552a848eSStefano Babic for (i = 0; i < count; i++) {
67*552a848eSStefano Babic mx7ulp_iomux_setup_pad(*p);
68*552a848eSStefano Babic p++;
69*552a848eSStefano Babic }
70*552a848eSStefano Babic }
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