1*552a848eSStefano Babic /*
2*552a848eSStefano Babic * Copyright 2015 Freescale Semiconductor, Inc.
3*552a848eSStefano Babic *
4*552a848eSStefano Babic * SPDX-License-Identifier: GPL-2.0+
5*552a848eSStefano Babic */
6*552a848eSStefano Babic
7*552a848eSStefano Babic #include <common.h>
8*552a848eSStefano Babic #include <asm/armv7.h>
9*552a848eSStefano Babic #include <asm/pl310.h>
10*552a848eSStefano Babic #include <asm/io.h>
11*552a848eSStefano Babic #include <asm/mach-imx/sys_proto.h>
12*552a848eSStefano Babic
13*552a848eSStefano Babic #ifndef CONFIG_SYS_DCACHE_OFF
enable_caches(void)14*552a848eSStefano Babic void enable_caches(void)
15*552a848eSStefano Babic {
16*552a848eSStefano Babic #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
17*552a848eSStefano Babic enum dcache_option option = DCACHE_WRITETHROUGH;
18*552a848eSStefano Babic #else
19*552a848eSStefano Babic enum dcache_option option = DCACHE_WRITEBACK;
20*552a848eSStefano Babic #endif
21*552a848eSStefano Babic /* Avoid random hang when download by usb */
22*552a848eSStefano Babic invalidate_dcache_all();
23*552a848eSStefano Babic
24*552a848eSStefano Babic /* Enable D-cache. I-cache is already enabled in start.S */
25*552a848eSStefano Babic dcache_enable();
26*552a848eSStefano Babic
27*552a848eSStefano Babic /* Enable caching on OCRAM and ROM */
28*552a848eSStefano Babic mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
29*552a848eSStefano Babic ROMCP_ARB_END_ADDR,
30*552a848eSStefano Babic option);
31*552a848eSStefano Babic mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
32*552a848eSStefano Babic IRAM_SIZE,
33*552a848eSStefano Babic option);
34*552a848eSStefano Babic }
35*552a848eSStefano Babic #endif
36*552a848eSStefano Babic
37*552a848eSStefano Babic #ifndef CONFIG_SYS_L2CACHE_OFF
38*552a848eSStefano Babic #ifdef CONFIG_SYS_L2_PL310
39*552a848eSStefano Babic #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
v7_outer_cache_enable(void)40*552a848eSStefano Babic void v7_outer_cache_enable(void)
41*552a848eSStefano Babic {
42*552a848eSStefano Babic struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
43*552a848eSStefano Babic struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
44*552a848eSStefano Babic unsigned int val;
45*552a848eSStefano Babic
46*552a848eSStefano Babic
47*552a848eSStefano Babic /*
48*552a848eSStefano Babic * Must disable the L2 before changing the latency parameters
49*552a848eSStefano Babic * and auxiliary control register.
50*552a848eSStefano Babic */
51*552a848eSStefano Babic clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
52*552a848eSStefano Babic
53*552a848eSStefano Babic /*
54*552a848eSStefano Babic * Set bit 22 in the auxiliary control register. If this bit
55*552a848eSStefano Babic * is cleared, PL310 treats Normal Shared Non-cacheable
56*552a848eSStefano Babic * accesses as Cacheable no-allocate.
57*552a848eSStefano Babic */
58*552a848eSStefano Babic setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
59*552a848eSStefano Babic
60*552a848eSStefano Babic if (is_mx6sl() || is_mx6sll()) {
61*552a848eSStefano Babic val = readl(&iomux->gpr[11]);
62*552a848eSStefano Babic if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
63*552a848eSStefano Babic /* L2 cache configured as OCRAM, reset it */
64*552a848eSStefano Babic val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
65*552a848eSStefano Babic writel(val, &iomux->gpr[11]);
66*552a848eSStefano Babic }
67*552a848eSStefano Babic }
68*552a848eSStefano Babic
69*552a848eSStefano Babic writel(0x132, &pl310->pl310_tag_latency_ctrl);
70*552a848eSStefano Babic writel(0x132, &pl310->pl310_data_latency_ctrl);
71*552a848eSStefano Babic
72*552a848eSStefano Babic val = readl(&pl310->pl310_prefetch_ctrl);
73*552a848eSStefano Babic
74*552a848eSStefano Babic /* Turn on the L2 I/D prefetch */
75*552a848eSStefano Babic val |= 0x30000000;
76*552a848eSStefano Babic
77*552a848eSStefano Babic /*
78*552a848eSStefano Babic * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
79*552a848eSStefano Babic * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
80*552a848eSStefano Babic * But according to ARM PL310 errata: 752271
81*552a848eSStefano Babic * ID: 752271: Double linefill feature can cause data corruption
82*552a848eSStefano Babic * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
83*552a848eSStefano Babic * Workaround: The only workaround to this erratum is to disable the
84*552a848eSStefano Babic * double linefill feature. This is the default behavior.
85*552a848eSStefano Babic */
86*552a848eSStefano Babic
87*552a848eSStefano Babic #ifndef CONFIG_MX6Q
88*552a848eSStefano Babic val |= 0x40800000;
89*552a848eSStefano Babic #endif
90*552a848eSStefano Babic writel(val, &pl310->pl310_prefetch_ctrl);
91*552a848eSStefano Babic
92*552a848eSStefano Babic val = readl(&pl310->pl310_power_ctrl);
93*552a848eSStefano Babic val |= L2X0_DYNAMIC_CLK_GATING_EN;
94*552a848eSStefano Babic val |= L2X0_STNDBY_MODE_EN;
95*552a848eSStefano Babic writel(val, &pl310->pl310_power_ctrl);
96*552a848eSStefano Babic
97*552a848eSStefano Babic setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
98*552a848eSStefano Babic }
99*552a848eSStefano Babic
v7_outer_cache_disable(void)100*552a848eSStefano Babic void v7_outer_cache_disable(void)
101*552a848eSStefano Babic {
102*552a848eSStefano Babic struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
103*552a848eSStefano Babic
104*552a848eSStefano Babic clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
105*552a848eSStefano Babic }
106*552a848eSStefano Babic #endif /* !CONFIG_SYS_L2_PL310 */
107*552a848eSStefano Babic #endif /* !CONFIG_SYS_L2CACHE_OFF */
108