xref: /rk3399_rockchip-uboot/arch/arm/mach-exynos/include/mach/ehci.h (revision 783983f323730540f861413dfbea6802c88afcf8)
1*77b55e8cSThomas Abraham /*
2*77b55e8cSThomas Abraham  * SAMSUNG EXYNOS USB HOST EHCI Controller
3*77b55e8cSThomas Abraham  *
4*77b55e8cSThomas Abraham  * Copyright (C) 2012 Samsung Electronics Co.Ltd
5*77b55e8cSThomas Abraham  *	Vivek Gautam <gautam.vivek@samsung.com>
6*77b55e8cSThomas Abraham  *
7*77b55e8cSThomas Abraham  * SPDX-License-Identifier:	GPL-2.0+
8*77b55e8cSThomas Abraham  */
9*77b55e8cSThomas Abraham 
10*77b55e8cSThomas Abraham #ifndef __ASM_ARM_ARCH_EHCI_H__
11*77b55e8cSThomas Abraham #define __ASM_ARM_ARCH_EHCI_H__
12*77b55e8cSThomas Abraham 
13*77b55e8cSThomas Abraham #define CLK_24MHZ		5
14*77b55e8cSThomas Abraham 
15*77b55e8cSThomas Abraham #define PHYPWR_NORMAL_MASK_PHY0                 (0x39 << 0)
16*77b55e8cSThomas Abraham #define PHYPWR_NORMAL_MASK_PHY1                 (0x7 << 6)
17*77b55e8cSThomas Abraham #define PHYPWR_NORMAL_MASK_HSIC0                (0x7 << 9)
18*77b55e8cSThomas Abraham #define PHYPWR_NORMAL_MASK_HSIC1                (0x7 << 12)
19*77b55e8cSThomas Abraham #define RSTCON_HOSTPHY_SWRST                    (0xf << 3)
20*77b55e8cSThomas Abraham #define RSTCON_SWRST                            (0x1 << 0)
21*77b55e8cSThomas Abraham 
22*77b55e8cSThomas Abraham #define HOST_CTRL0_PHYSWRSTALL			(1 << 31)
23*77b55e8cSThomas Abraham #define HOST_CTRL0_COMMONON_N			(1 << 9)
24*77b55e8cSThomas Abraham #define HOST_CTRL0_SIDDQ			(1 << 6)
25*77b55e8cSThomas Abraham #define HOST_CTRL0_FORCESLEEP			(1 << 5)
26*77b55e8cSThomas Abraham #define HOST_CTRL0_FORCESUSPEND			(1 << 4)
27*77b55e8cSThomas Abraham #define HOST_CTRL0_WORDINTERFACE		(1 << 3)
28*77b55e8cSThomas Abraham #define HOST_CTRL0_UTMISWRST			(1 << 2)
29*77b55e8cSThomas Abraham #define HOST_CTRL0_LINKSWRST			(1 << 1)
30*77b55e8cSThomas Abraham #define HOST_CTRL0_PHYSWRST			(1 << 0)
31*77b55e8cSThomas Abraham 
32*77b55e8cSThomas Abraham #define HOST_CTRL0_FSEL_MASK			(7 << 16)
33*77b55e8cSThomas Abraham 
34*77b55e8cSThomas Abraham #define EHCICTRL_ENAINCRXALIGN			(1 << 29)
35*77b55e8cSThomas Abraham #define EHCICTRL_ENAINCR4			(1 << 28)
36*77b55e8cSThomas Abraham #define EHCICTRL_ENAINCR8			(1 << 27)
37*77b55e8cSThomas Abraham #define EHCICTRL_ENAINCR16			(1 << 26)
38*77b55e8cSThomas Abraham 
39*77b55e8cSThomas Abraham #define HSIC_CTRL_REFCLKSEL                     (0x2)
40*77b55e8cSThomas Abraham #define HSIC_CTRL_REFCLKSEL_MASK                (0x3)
41*77b55e8cSThomas Abraham #define HSIC_CTRL_REFCLKSEL_SHIFT               (23)
42*77b55e8cSThomas Abraham 
43*77b55e8cSThomas Abraham #define HSIC_CTRL_REFCLKDIV_12                  (0x24)
44*77b55e8cSThomas Abraham #define HSIC_CTRL_REFCLKDIV_MASK                (0x7f)
45*77b55e8cSThomas Abraham #define HSIC_CTRL_REFCLKDIV_SHIFT               (16)
46*77b55e8cSThomas Abraham 
47*77b55e8cSThomas Abraham #define HSIC_CTRL_SIDDQ                         (0x1 << 6)
48*77b55e8cSThomas Abraham #define HSIC_CTRL_FORCESLEEP                    (0x1 << 5)
49*77b55e8cSThomas Abraham #define HSIC_CTRL_FORCESUSPEND                  (0x1 << 4)
50*77b55e8cSThomas Abraham #define HSIC_CTRL_UTMISWRST                     (0x1 << 2)
51*77b55e8cSThomas Abraham #define HSIC_CTRL_PHYSWRST                      (0x1 << 0)
52*77b55e8cSThomas Abraham 
53*77b55e8cSThomas Abraham /* Register map for PHY control */
54*77b55e8cSThomas Abraham struct exynos_usb_phy {
55*77b55e8cSThomas Abraham 	unsigned int usbphyctrl0;
56*77b55e8cSThomas Abraham 	unsigned int usbphytune0;
57*77b55e8cSThomas Abraham 	unsigned int reserved1[2];
58*77b55e8cSThomas Abraham 	unsigned int hsicphyctrl1;
59*77b55e8cSThomas Abraham 	unsigned int hsicphytune1;
60*77b55e8cSThomas Abraham 	unsigned int reserved2[2];
61*77b55e8cSThomas Abraham 	unsigned int hsicphyctrl2;
62*77b55e8cSThomas Abraham 	unsigned int hsicphytune2;
63*77b55e8cSThomas Abraham 	unsigned int reserved3[2];
64*77b55e8cSThomas Abraham 	unsigned int ehcictrl;
65*77b55e8cSThomas Abraham 	unsigned int ohcictrl;
66*77b55e8cSThomas Abraham 	unsigned int usbotgsys;
67*77b55e8cSThomas Abraham 	unsigned int reserved4;
68*77b55e8cSThomas Abraham 	unsigned int usbotgtune;
69*77b55e8cSThomas Abraham };
70*77b55e8cSThomas Abraham 
71*77b55e8cSThomas Abraham struct exynos4412_usb_phy {
72*77b55e8cSThomas Abraham 	unsigned int usbphyctrl;
73*77b55e8cSThomas Abraham 	unsigned int usbphyclk;
74*77b55e8cSThomas Abraham 	unsigned int usbphyrstcon;
75*77b55e8cSThomas Abraham };
76*77b55e8cSThomas Abraham 
77*77b55e8cSThomas Abraham /* Switch on the VBUS power. */
78*77b55e8cSThomas Abraham int board_usb_vbus_init(void);
79*77b55e8cSThomas Abraham 
80*77b55e8cSThomas Abraham #endif /* __ASM_ARM_ARCH_EHCI_H__ */
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