1*3d357619SMasahiro Yamada /* 2*3d357619SMasahiro Yamada * Copyright (C) 2011 3*3d357619SMasahiro Yamada * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4*3d357619SMasahiro Yamada * 5*3d357619SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 6*3d357619SMasahiro Yamada */ 7*3d357619SMasahiro Yamada #ifndef _DV_SYSCFG_DEFS_H_ 8*3d357619SMasahiro Yamada #define _DV_SYSCFG_DEFS_H_ 9*3d357619SMasahiro Yamada 10*3d357619SMasahiro Yamada #ifndef CONFIG_SOC_DA8XX 11*3d357619SMasahiro Yamada /* System Control Module register structure for DM365 */ 12*3d357619SMasahiro Yamada struct dv_sys_module_regs { 13*3d357619SMasahiro Yamada unsigned int pinmux[5]; /* 0x00 */ 14*3d357619SMasahiro Yamada unsigned int bootcfg; /* 0x14 */ 15*3d357619SMasahiro Yamada unsigned int arm_intmux; /* 0x18 */ 16*3d357619SMasahiro Yamada unsigned int edma_evtmux; /* 0x1C */ 17*3d357619SMasahiro Yamada unsigned int ddr_slew; /* 0x20 */ 18*3d357619SMasahiro Yamada unsigned int clkout; /* 0x24 */ 19*3d357619SMasahiro Yamada unsigned int device_id; /* 0x28 */ 20*3d357619SMasahiro Yamada unsigned int vdac_config; /* 0x2C */ 21*3d357619SMasahiro Yamada unsigned int timer64_ctl; /* 0x30 */ 22*3d357619SMasahiro Yamada unsigned int usbbphy_ctl; /* 0x34 */ 23*3d357619SMasahiro Yamada unsigned int misc; /* 0x38 */ 24*3d357619SMasahiro Yamada unsigned int mstpri[2]; /* 0x3C */ 25*3d357619SMasahiro Yamada unsigned int vpss_clkctl; /* 0x44 */ 26*3d357619SMasahiro Yamada unsigned int peri_clkctl; /* 0x48 */ 27*3d357619SMasahiro Yamada unsigned int deepsleep; /* 0x4C */ 28*3d357619SMasahiro Yamada unsigned int dft_enable; /* 0x50 */ 29*3d357619SMasahiro Yamada unsigned int debounce[8]; /* 0x54 */ 30*3d357619SMasahiro Yamada unsigned int vtpiocr; /* 0x74 */ 31*3d357619SMasahiro Yamada unsigned int pupdctl0; /* 0x78 */ 32*3d357619SMasahiro Yamada unsigned int pupdctl1; /* 0x7C */ 33*3d357619SMasahiro Yamada unsigned int hdimcopbt; /* 0x80 */ 34*3d357619SMasahiro Yamada unsigned int pll0_config; /* 0x84 */ 35*3d357619SMasahiro Yamada unsigned int pll1_config; /* 0x88 */ 36*3d357619SMasahiro Yamada }; 37*3d357619SMasahiro Yamada 38*3d357619SMasahiro Yamada #define VPTIO_RDY (1 << 15) 39*3d357619SMasahiro Yamada #define VPTIO_IOPWRDN (1 << 14) 40*3d357619SMasahiro Yamada #define VPTIO_CLRZ (1 << 13) 41*3d357619SMasahiro Yamada #define VPTIO_LOCK (1 << 7) 42*3d357619SMasahiro Yamada #define VPTIO_PWRDN (1 << 6) 43*3d357619SMasahiro Yamada 44*3d357619SMasahiro Yamada #define VPSS_CLK_CTL_VPSS_CLKMD (1 << 7) 45*3d357619SMasahiro Yamada 46*3d357619SMasahiro Yamada #define dv_sys_module_regs \ 47*3d357619SMasahiro Yamada ((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE) 48*3d357619SMasahiro Yamada 49*3d357619SMasahiro Yamada #endif /* !CONFIG_SOC_DA8XX */ 50*3d357619SMasahiro Yamada #endif /* _DV_SYSCFG_DEFS_H_ */ 51