1*3d357619SMasahiro Yamada /* 2*3d357619SMasahiro Yamada * Copyright (C) 2011 3*3d357619SMasahiro Yamada * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4*3d357619SMasahiro Yamada * 5*3d357619SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 6*3d357619SMasahiro Yamada */ 7*3d357619SMasahiro Yamada #ifndef _DV_PSC_DEFS_H_ 8*3d357619SMasahiro Yamada #define _DV_PSC_DEFS_H_ 9*3d357619SMasahiro Yamada 10*3d357619SMasahiro Yamada /* 11*3d357619SMasahiro Yamada * Power/Sleep Ctrl Register structure 12*3d357619SMasahiro Yamada * See sprufb3.pdf, Chapter 7 13*3d357619SMasahiro Yamada */ 14*3d357619SMasahiro Yamada struct dv_psc_regs { 15*3d357619SMasahiro Yamada unsigned int pid; /* 0x000 */ 16*3d357619SMasahiro Yamada unsigned char rsvd0[16]; /* 0x004 */ 17*3d357619SMasahiro Yamada unsigned char rsvd1[4]; /* 0x014 */ 18*3d357619SMasahiro Yamada unsigned int inteval; /* 0x018 */ 19*3d357619SMasahiro Yamada unsigned char rsvd2[36]; /* 0x01C */ 20*3d357619SMasahiro Yamada unsigned int merrpr0; /* 0x040 */ 21*3d357619SMasahiro Yamada unsigned int merrpr1; /* 0x044 */ 22*3d357619SMasahiro Yamada unsigned char rsvd3[8]; /* 0x048 */ 23*3d357619SMasahiro Yamada unsigned int merrcr0; /* 0x050 */ 24*3d357619SMasahiro Yamada unsigned int merrcr1; /* 0x054 */ 25*3d357619SMasahiro Yamada unsigned char rsvd4[8]; /* 0x058 */ 26*3d357619SMasahiro Yamada unsigned int perrpr; /* 0x060 */ 27*3d357619SMasahiro Yamada unsigned char rsvd5[4]; /* 0x064 */ 28*3d357619SMasahiro Yamada unsigned int perrcr; /* 0x068 */ 29*3d357619SMasahiro Yamada unsigned char rsvd6[4]; /* 0x06C */ 30*3d357619SMasahiro Yamada unsigned int epcpr; /* 0x070 */ 31*3d357619SMasahiro Yamada unsigned char rsvd7[4]; /* 0x074 */ 32*3d357619SMasahiro Yamada unsigned int epccr; /* 0x078 */ 33*3d357619SMasahiro Yamada unsigned char rsvd8[144]; /* 0x07C */ 34*3d357619SMasahiro Yamada unsigned char rsvd9[20]; /* 0x10C */ 35*3d357619SMasahiro Yamada unsigned int ptcmd; /* 0x120 */ 36*3d357619SMasahiro Yamada unsigned char rsvd10[4]; /* 0x124 */ 37*3d357619SMasahiro Yamada unsigned int ptstat; /* 0x128 */ 38*3d357619SMasahiro Yamada unsigned char rsvd11[212]; /* 0x12C */ 39*3d357619SMasahiro Yamada unsigned int pdstat0; /* 0x200 */ 40*3d357619SMasahiro Yamada unsigned int pdstat1; /* 0x204 */ 41*3d357619SMasahiro Yamada unsigned char rsvd12[248]; /* 0x208 */ 42*3d357619SMasahiro Yamada unsigned int pdctl0; /* 0x300 */ 43*3d357619SMasahiro Yamada unsigned int pdctl1; /* 0x304 */ 44*3d357619SMasahiro Yamada unsigned char rsvd13[536]; /* 0x308 */ 45*3d357619SMasahiro Yamada unsigned int mckout0; /* 0x520 */ 46*3d357619SMasahiro Yamada unsigned int mckout1; /* 0x524 */ 47*3d357619SMasahiro Yamada unsigned char rsvd14[728]; /* 0x528 */ 48*3d357619SMasahiro Yamada unsigned int mdstat[52]; /* 0x800 */ 49*3d357619SMasahiro Yamada unsigned char rsvd15[304]; /* 0x8D0 */ 50*3d357619SMasahiro Yamada unsigned int mdctl[52]; /* 0xA00 */ 51*3d357619SMasahiro Yamada }; 52*3d357619SMasahiro Yamada 53*3d357619SMasahiro Yamada /* PSC constants */ 54*3d357619SMasahiro Yamada #define EMURSTIE_MASK (0x00000200) 55*3d357619SMasahiro Yamada 56*3d357619SMasahiro Yamada #define PD0 (0) 57*3d357619SMasahiro Yamada 58*3d357619SMasahiro Yamada #define PSC_ENABLE (0x3) 59*3d357619SMasahiro Yamada #define PSC_DISABLE (0x2) 60*3d357619SMasahiro Yamada #define PSC_SYNCRESET (0x1) 61*3d357619SMasahiro Yamada #define PSC_SWRSTDISABLE (0x0) 62*3d357619SMasahiro Yamada 63*3d357619SMasahiro Yamada #define PSC_GOSTAT (1 << 0) 64*3d357619SMasahiro Yamada #define PSC_MD_STATE_MSK (0x1f) 65*3d357619SMasahiro Yamada 66*3d357619SMasahiro Yamada #define PSC_CMD_GO (1 << 0) 67*3d357619SMasahiro Yamada 68*3d357619SMasahiro Yamada #define dv_psc_regs ((struct dv_psc_regs *)DAVINCI_PWR_SLEEP_CNTRL_BASE) 69*3d357619SMasahiro Yamada 70*3d357619SMasahiro Yamada #endif /* _DV_PSC_DEFS_H_ */ 71