1*3d357619SMasahiro Yamada /* 2*3d357619SMasahiro Yamada * Copyright (C) 2009 Texas Instruments Incorporated 3*3d357619SMasahiro Yamada * 4*3d357619SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 5*3d357619SMasahiro Yamada */ 6*3d357619SMasahiro Yamada #ifndef _GPIO_DEFS_H_ 7*3d357619SMasahiro Yamada #define _GPIO_DEFS_H_ 8*3d357619SMasahiro Yamada 9*3d357619SMasahiro Yamada #ifndef CONFIG_SOC_DA8XX 10*3d357619SMasahiro Yamada #define DAVINCI_GPIO_BINTEN 0x01C67008 11*3d357619SMasahiro Yamada #define DAVINCI_GPIO_BANK01 0x01C67010 12*3d357619SMasahiro Yamada #define DAVINCI_GPIO_BANK23 0x01C67038 13*3d357619SMasahiro Yamada #define DAVINCI_GPIO_BANK45 0x01C67060 14*3d357619SMasahiro Yamada #define DAVINCI_GPIO_BANK67 0x01C67088 15*3d357619SMasahiro Yamada 16*3d357619SMasahiro Yamada #else /* CONFIG_SOC_DA8XX */ 17*3d357619SMasahiro Yamada #define DAVINCI_GPIO_BINTEN 0x01E26008 18*3d357619SMasahiro Yamada #define DAVINCI_GPIO_BANK01 0x01E26010 19*3d357619SMasahiro Yamada #define DAVINCI_GPIO_BANK23 0x01E26038 20*3d357619SMasahiro Yamada #define DAVINCI_GPIO_BANK45 0x01E26060 21*3d357619SMasahiro Yamada #define DAVINCI_GPIO_BANK67 0x01E26088 22*3d357619SMasahiro Yamada #define DAVINCI_GPIO_BANK8 0x01E260B0 23*3d357619SMasahiro Yamada #endif /* CONFIG_SOC_DA8XX */ 24*3d357619SMasahiro Yamada 25*3d357619SMasahiro Yamada struct davinci_gpio { 26*3d357619SMasahiro Yamada unsigned int dir; 27*3d357619SMasahiro Yamada unsigned int out_data; 28*3d357619SMasahiro Yamada unsigned int set_data; 29*3d357619SMasahiro Yamada unsigned int clr_data; 30*3d357619SMasahiro Yamada unsigned int in_data; 31*3d357619SMasahiro Yamada unsigned int set_rising; 32*3d357619SMasahiro Yamada unsigned int clr_rising; 33*3d357619SMasahiro Yamada unsigned int set_falling; 34*3d357619SMasahiro Yamada unsigned int clr_falling; 35*3d357619SMasahiro Yamada unsigned int intstat; 36*3d357619SMasahiro Yamada }; 37*3d357619SMasahiro Yamada 38*3d357619SMasahiro Yamada struct davinci_gpio_bank { 39*3d357619SMasahiro Yamada int num_gpio; 40*3d357619SMasahiro Yamada unsigned int irq_num; 41*3d357619SMasahiro Yamada unsigned int irq_mask; 42*3d357619SMasahiro Yamada unsigned long *in_use; 43*3d357619SMasahiro Yamada unsigned long base; 44*3d357619SMasahiro Yamada }; 45*3d357619SMasahiro Yamada 46*3d357619SMasahiro Yamada #define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01) 47*3d357619SMasahiro Yamada #define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23) 48*3d357619SMasahiro Yamada #define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45) 49*3d357619SMasahiro Yamada #define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67) 50*3d357619SMasahiro Yamada #define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8) 51*3d357619SMasahiro Yamada 52*3d357619SMasahiro Yamada #define gpio_status() gpio_info() 53*3d357619SMasahiro Yamada #define GPIO_NAME_SIZE 20 54*3d357619SMasahiro Yamada #if defined(CONFIG_SOC_DM644X) 55*3d357619SMasahiro Yamada /* GPIO0 to GPIO53, omit the V3.3 volts one */ 56*3d357619SMasahiro Yamada #define MAX_NUM_GPIOS 70 57*3d357619SMasahiro Yamada #elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850) 58*3d357619SMasahiro Yamada #define MAX_NUM_GPIOS 128 59*3d357619SMasahiro Yamada #else 60*3d357619SMasahiro Yamada #define MAX_NUM_GPIOS 144 61*3d357619SMasahiro Yamada #endif 62*3d357619SMasahiro Yamada #define GPIO_BANK(gp) (davinci_gpio_bank01 + ((gp) >> 5)) 63*3d357619SMasahiro Yamada #define GPIO_BIT(gp) ((gp) & 0x1F) 64*3d357619SMasahiro Yamada 65*3d357619SMasahiro Yamada void gpio_info(void); 66*3d357619SMasahiro Yamada 67*3d357619SMasahiro Yamada #endif 68