1*3d357619SMasahiro Yamada /* 2*3d357619SMasahiro Yamada * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 3*3d357619SMasahiro Yamada * 4*3d357619SMasahiro Yamada * Based on: 5*3d357619SMasahiro Yamada * 6*3d357619SMasahiro Yamada * ---------------------------------------------------------------------------- 7*3d357619SMasahiro Yamada * 8*3d357619SMasahiro Yamada * dm644x_emac.h 9*3d357619SMasahiro Yamada * 10*3d357619SMasahiro Yamada * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM 11*3d357619SMasahiro Yamada * 12*3d357619SMasahiro Yamada * Copyright (C) 2005 Texas Instruments. 13*3d357619SMasahiro Yamada * 14*3d357619SMasahiro Yamada * ---------------------------------------------------------------------------- 15*3d357619SMasahiro Yamada * 16*3d357619SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 17*3d357619SMasahiro Yamada * 18*3d357619SMasahiro Yamada * Modifications: 19*3d357619SMasahiro Yamada * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot. 20*3d357619SMasahiro Yamada */ 21*3d357619SMasahiro Yamada 22*3d357619SMasahiro Yamada #ifndef _DM644X_EMAC_H_ 23*3d357619SMasahiro Yamada #define _DM644X_EMAC_H_ 24*3d357619SMasahiro Yamada 25*3d357619SMasahiro Yamada #include <asm/arch/hardware.h> 26*3d357619SMasahiro Yamada 27*3d357619SMasahiro Yamada #ifdef CONFIG_SOC_DM365 28*3d357619SMasahiro Yamada #define EMAC_BASE_ADDR (0x01d07000) 29*3d357619SMasahiro Yamada #define EMAC_WRAPPER_BASE_ADDR (0x01d0a000) 30*3d357619SMasahiro Yamada #define EMAC_WRAPPER_RAM_ADDR (0x01d08000) 31*3d357619SMasahiro Yamada #define EMAC_MDIO_BASE_ADDR (0x01d0b000) 32*3d357619SMasahiro Yamada #define DAVINCI_EMAC_VERSION2 33*3d357619SMasahiro Yamada #elif defined(CONFIG_SOC_DA8XX) 34*3d357619SMasahiro Yamada #define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE 35*3d357619SMasahiro Yamada #define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 36*3d357619SMasahiro Yamada #define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE 37*3d357619SMasahiro Yamada #define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE 38*3d357619SMasahiro Yamada #define DAVINCI_EMAC_VERSION2 39*3d357619SMasahiro Yamada #else 40*3d357619SMasahiro Yamada #define EMAC_BASE_ADDR (0x01c80000) 41*3d357619SMasahiro Yamada #define EMAC_WRAPPER_BASE_ADDR (0x01c81000) 42*3d357619SMasahiro Yamada #define EMAC_WRAPPER_RAM_ADDR (0x01c82000) 43*3d357619SMasahiro Yamada #define EMAC_MDIO_BASE_ADDR (0x01c84000) 44*3d357619SMasahiro Yamada #endif 45*3d357619SMasahiro Yamada 46*3d357619SMasahiro Yamada #ifdef CONFIG_SOC_DM646X 47*3d357619SMasahiro Yamada #define DAVINCI_EMAC_VERSION2 48*3d357619SMasahiro Yamada #define DAVINCI_EMAC_GIG_ENABLE 49*3d357619SMasahiro Yamada #endif 50*3d357619SMasahiro Yamada 51*3d357619SMasahiro Yamada #ifdef CONFIG_SOC_DM646X 52*3d357619SMasahiro Yamada /* MDIO module input frequency */ 53*3d357619SMasahiro Yamada #define EMAC_MDIO_BUS_FREQ 76500000 54*3d357619SMasahiro Yamada /* MDIO clock output frequency */ 55*3d357619SMasahiro Yamada #define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */ 56*3d357619SMasahiro Yamada #elif defined(CONFIG_SOC_DM365) 57*3d357619SMasahiro Yamada /* MDIO module input frequency */ 58*3d357619SMasahiro Yamada #define EMAC_MDIO_BUS_FREQ 121500000 59*3d357619SMasahiro Yamada /* MDIO clock output frequency */ 60*3d357619SMasahiro Yamada #define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */ 61*3d357619SMasahiro Yamada #elif defined(CONFIG_SOC_DA8XX) 62*3d357619SMasahiro Yamada /* MDIO module input frequency */ 63*3d357619SMasahiro Yamada #define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID) 64*3d357619SMasahiro Yamada /* MDIO clock output frequency */ 65*3d357619SMasahiro Yamada #define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ 66*3d357619SMasahiro Yamada #else 67*3d357619SMasahiro Yamada /* MDIO module input frequency */ 68*3d357619SMasahiro Yamada #define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */ 69*3d357619SMasahiro Yamada /* MDIO clock output frequency */ 70*3d357619SMasahiro Yamada #define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ 71*3d357619SMasahiro Yamada #endif 72*3d357619SMasahiro Yamada 73*3d357619SMasahiro Yamada #define PHY_KSZ8873 (0x00221450) 74*3d357619SMasahiro Yamada int ksz8873_is_phy_connected(int phy_addr); 75*3d357619SMasahiro Yamada int ksz8873_get_link_speed(int phy_addr); 76*3d357619SMasahiro Yamada int ksz8873_init_phy(int phy_addr); 77*3d357619SMasahiro Yamada int ksz8873_auto_negotiate(int phy_addr); 78*3d357619SMasahiro Yamada 79*3d357619SMasahiro Yamada #define PHY_LXT972 (0x001378e2) 80*3d357619SMasahiro Yamada int lxt972_is_phy_connected(int phy_addr); 81*3d357619SMasahiro Yamada int lxt972_get_link_speed(int phy_addr); 82*3d357619SMasahiro Yamada int lxt972_init_phy(int phy_addr); 83*3d357619SMasahiro Yamada int lxt972_auto_negotiate(int phy_addr); 84*3d357619SMasahiro Yamada 85*3d357619SMasahiro Yamada #define PHY_DP83848 (0x20005c90) 86*3d357619SMasahiro Yamada int dp83848_is_phy_connected(int phy_addr); 87*3d357619SMasahiro Yamada int dp83848_get_link_speed(int phy_addr); 88*3d357619SMasahiro Yamada int dp83848_init_phy(int phy_addr); 89*3d357619SMasahiro Yamada int dp83848_auto_negotiate(int phy_addr); 90*3d357619SMasahiro Yamada 91*3d357619SMasahiro Yamada #define PHY_ET1011C (0x282f013) 92*3d357619SMasahiro Yamada int et1011c_get_link_speed(int phy_addr); 93*3d357619SMasahiro Yamada 94*3d357619SMasahiro Yamada #endif /* _DM644X_EMAC_H_ */ 95