1*3d357619SMasahiro Yamada /* 2*3d357619SMasahiro Yamada * Copyright (C) 2011 3*3d357619SMasahiro Yamada * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4*3d357619SMasahiro Yamada * 5*3d357619SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 6*3d357619SMasahiro Yamada */ 7*3d357619SMasahiro Yamada #ifndef _DV_DDR2_DEFS_H_ 8*3d357619SMasahiro Yamada #define _DV_DDR2_DEFS_H_ 9*3d357619SMasahiro Yamada 10*3d357619SMasahiro Yamada /* 11*3d357619SMasahiro Yamada * DDR2 Memory Ctrl Register structure 12*3d357619SMasahiro Yamada * See sprueh7d.pdf for more details. 13*3d357619SMasahiro Yamada */ 14*3d357619SMasahiro Yamada struct dv_ddr2_regs_ctrl { 15*3d357619SMasahiro Yamada unsigned char rsvd0[4]; /* 0x00 */ 16*3d357619SMasahiro Yamada unsigned int sdrstat; /* 0x04 */ 17*3d357619SMasahiro Yamada unsigned int sdbcr; /* 0x08 */ 18*3d357619SMasahiro Yamada unsigned int sdrcr; /* 0x0C */ 19*3d357619SMasahiro Yamada unsigned int sdtimr; /* 0x10 */ 20*3d357619SMasahiro Yamada unsigned int sdtimr2; /* 0x14 */ 21*3d357619SMasahiro Yamada unsigned char rsvd1[4]; /* 0x18 */ 22*3d357619SMasahiro Yamada unsigned int sdbcr2; /* 0x1C */ 23*3d357619SMasahiro Yamada unsigned int pbbpr; /* 0x20 */ 24*3d357619SMasahiro Yamada unsigned char rsvd2[156]; /* 0x24 */ 25*3d357619SMasahiro Yamada unsigned int irr; /* 0xC0 */ 26*3d357619SMasahiro Yamada unsigned int imr; /* 0xC4 */ 27*3d357619SMasahiro Yamada unsigned int imsr; /* 0xC8 */ 28*3d357619SMasahiro Yamada unsigned int imcr; /* 0xCC */ 29*3d357619SMasahiro Yamada unsigned char rsvd3[20]; /* 0xD0 */ 30*3d357619SMasahiro Yamada unsigned int ddrphycr; /* 0xE4 */ 31*3d357619SMasahiro Yamada unsigned int ddrphycr2; /* 0xE8 */ 32*3d357619SMasahiro Yamada unsigned char rsvd4[4]; /* 0xEC */ 33*3d357619SMasahiro Yamada }; 34*3d357619SMasahiro Yamada 35*3d357619SMasahiro Yamada #define DV_DDR_PHY_PWRDNEN 0x40 36*3d357619SMasahiro Yamada #define DV_DDR_PHY_EXT_STRBEN 0x80 37*3d357619SMasahiro Yamada #define DV_DDR_PHY_RD_LATENCY_SHIFT 0 38*3d357619SMasahiro Yamada 39*3d357619SMasahiro Yamada #define DV_DDR_SDTMR1_RFC_SHIFT 25 40*3d357619SMasahiro Yamada #define DV_DDR_SDTMR1_RP_SHIFT 22 41*3d357619SMasahiro Yamada #define DV_DDR_SDTMR1_RCD_SHIFT 19 42*3d357619SMasahiro Yamada #define DV_DDR_SDTMR1_WR_SHIFT 16 43*3d357619SMasahiro Yamada #define DV_DDR_SDTMR1_RAS_SHIFT 11 44*3d357619SMasahiro Yamada #define DV_DDR_SDTMR1_RC_SHIFT 6 45*3d357619SMasahiro Yamada #define DV_DDR_SDTMR1_RRD_SHIFT 3 46*3d357619SMasahiro Yamada #define DV_DDR_SDTMR1_WTR_SHIFT 0 47*3d357619SMasahiro Yamada 48*3d357619SMasahiro Yamada #define DV_DDR_SDTMR2_RASMAX_SHIFT 27 49*3d357619SMasahiro Yamada #define DV_DDR_SDTMR2_XP_SHIFT 25 50*3d357619SMasahiro Yamada #define DV_DDR_SDTMR2_ODT_SHIFT 23 51*3d357619SMasahiro Yamada #define DV_DDR_SDTMR2_XSNR_SHIFT 16 52*3d357619SMasahiro Yamada #define DV_DDR_SDTMR2_XSRD_SHIFT 8 53*3d357619SMasahiro Yamada #define DV_DDR_SDTMR2_RTP_SHIFT 5 54*3d357619SMasahiro Yamada #define DV_DDR_SDTMR2_CKE_SHIFT 0 55*3d357619SMasahiro Yamada 56*3d357619SMasahiro Yamada #define DV_DDR_SDCR_DDR2TERM1_SHIFT 27 57*3d357619SMasahiro Yamada #define DV_DDR_SDCR_IBANK_POS_SHIFT 26 58*3d357619SMasahiro Yamada #define DV_DDR_SDCR_MSDRAMEN_SHIFT 25 59*3d357619SMasahiro Yamada #define DV_DDR_SDCR_DDRDRIVE1_SHIFT 24 60*3d357619SMasahiro Yamada #define DV_DDR_SDCR_BOOTUNLOCK_SHIFT 23 61*3d357619SMasahiro Yamada #define DV_DDR_SDCR_DDR_DDQS_SHIFT 22 62*3d357619SMasahiro Yamada #define DV_DDR_SDCR_DDR2EN_SHIFT 20 63*3d357619SMasahiro Yamada #define DV_DDR_SDCR_DDRDRIVE0_SHIFT 18 64*3d357619SMasahiro Yamada #define DV_DDR_SDCR_DDREN_SHIFT 17 65*3d357619SMasahiro Yamada #define DV_DDR_SDCR_SDRAMEN_SHIFT 16 66*3d357619SMasahiro Yamada #define DV_DDR_SDCR_TIMUNLOCK_SHIFT 15 67*3d357619SMasahiro Yamada #define DV_DDR_SDCR_BUS_WIDTH_SHIFT 14 68*3d357619SMasahiro Yamada #define DV_DDR_SDCR_CL_SHIFT 9 69*3d357619SMasahiro Yamada #define DV_DDR_SDCR_IBANK_SHIFT 4 70*3d357619SMasahiro Yamada #define DV_DDR_SDCR_PAGESIZE_SHIFT 0 71*3d357619SMasahiro Yamada 72*3d357619SMasahiro Yamada #define DV_DDR_SDRCR_LPMODEN (1 << 31) 73*3d357619SMasahiro Yamada #define DV_DDR_SDRCR_MCLKSTOPEN (1 << 30) 74*3d357619SMasahiro Yamada 75*3d357619SMasahiro Yamada #define DV_DDR_SRCR_LPMODEN_SHIFT 31 76*3d357619SMasahiro Yamada #define DV_DDR_SRCR_MCLKSTOPEN_SHIFT 30 77*3d357619SMasahiro Yamada 78*3d357619SMasahiro Yamada #define DV_DDR_BOOTUNLOCK (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT) 79*3d357619SMasahiro Yamada #define DV_DDR_TIMUNLOCK (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) 80*3d357619SMasahiro Yamada 81*3d357619SMasahiro Yamada #define dv_ddr2_regs_ctrl \ 82*3d357619SMasahiro Yamada ((struct dv_ddr2_regs_ctrl *)DAVINCI_DDR_EMIF_CTRL_BASE) 83*3d357619SMasahiro Yamada 84*3d357619SMasahiro Yamada #endif /* _DV_DDR2_DEFS_H_ */ 85