xref: /rk3399_rockchip-uboot/arch/arm/mach-bcm283x/include/mach/timer.h (revision d6c418e4b8036038505ac67bf5d85a19ca2c650d)
1*d6c418e4SMasahiro Yamada /*
2*d6c418e4SMasahiro Yamada  * (C) Copyright 2012,2015 Stephen Warren
3*d6c418e4SMasahiro Yamada  *
4*d6c418e4SMasahiro Yamada  * SPDX-License-Identifier:	GPL-2.0
5*d6c418e4SMasahiro Yamada  */
6*d6c418e4SMasahiro Yamada 
7*d6c418e4SMasahiro Yamada #ifndef _BCM2835_TIMER_H
8*d6c418e4SMasahiro Yamada #define _BCM2835_TIMER_H
9*d6c418e4SMasahiro Yamada 
10*d6c418e4SMasahiro Yamada #ifdef CONFIG_BCM2836
11*d6c418e4SMasahiro Yamada #define BCM2835_TIMER_PHYSADDR	0x3f003000
12*d6c418e4SMasahiro Yamada #else
13*d6c418e4SMasahiro Yamada #define BCM2835_TIMER_PHYSADDR	0x20003000
14*d6c418e4SMasahiro Yamada #endif
15*d6c418e4SMasahiro Yamada 
16*d6c418e4SMasahiro Yamada struct bcm2835_timer_regs {
17*d6c418e4SMasahiro Yamada 	u32 cs;
18*d6c418e4SMasahiro Yamada 	u32 clo;
19*d6c418e4SMasahiro Yamada 	u32 chi;
20*d6c418e4SMasahiro Yamada 	u32 c0;
21*d6c418e4SMasahiro Yamada 	u32 c1;
22*d6c418e4SMasahiro Yamada 	u32 c2;
23*d6c418e4SMasahiro Yamada 	u32 c3;
24*d6c418e4SMasahiro Yamada };
25*d6c418e4SMasahiro Yamada 
26*d6c418e4SMasahiro Yamada #define BCM2835_TIMER_CS_M3	(1 << 3)
27*d6c418e4SMasahiro Yamada #define BCM2835_TIMER_CS_M2	(1 << 2)
28*d6c418e4SMasahiro Yamada #define BCM2835_TIMER_CS_M1	(1 << 1)
29*d6c418e4SMasahiro Yamada #define BCM2835_TIMER_CS_M0	(1 << 0)
30*d6c418e4SMasahiro Yamada 
31*d6c418e4SMasahiro Yamada extern ulong get_timer_us(ulong base);
32*d6c418e4SMasahiro Yamada 
33*d6c418e4SMasahiro Yamada #endif
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