1*af930827SMasahiro Yamada /* 2*af930827SMasahiro Yamada * Bus Matrix header file for the SAMA5 family 3*af930827SMasahiro Yamada * 4*af930827SMasahiro Yamada * Copyright (C) 2014 Atmel 5*af930827SMasahiro Yamada * Bo Shen <voice.shen@atmel.com> 6*af930827SMasahiro Yamada * 7*af930827SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 8*af930827SMasahiro Yamada */ 9*af930827SMasahiro Yamada 10*af930827SMasahiro Yamada #ifndef __SAMA5_MATRIX_H 11*af930827SMasahiro Yamada #define __SAMA5_MATRIX_H 12*af930827SMasahiro Yamada 13*af930827SMasahiro Yamada struct atmel_matrix { 14*af930827SMasahiro Yamada u32 mcfg[16]; /* 0x00 ~ 0x3c: Master Configuration Register */ 15*af930827SMasahiro Yamada u32 scfg[16]; /* 0x40 ~ 0x7c: Slave Configuration Register */ 16*af930827SMasahiro Yamada u32 pras[16][2];/* 0x80 ~ 0xfc: Priority Register A/B */ 17*af930827SMasahiro Yamada u32 res1[20]; /* 0x100 ~ 0x14c */ 18*af930827SMasahiro Yamada u32 meier; /* 0x150: Master Error Interrupt Enable Register */ 19*af930827SMasahiro Yamada u32 meidr; /* 0x154: Master Error Interrupt Disable Register */ 20*af930827SMasahiro Yamada u32 meimr; /* 0x158: Master Error Interrupt Mask Register */ 21*af930827SMasahiro Yamada u32 mesr; /* 0x15c: Master Error Status Register */ 22*af930827SMasahiro Yamada u32 mear[16]; /* 0x160 ~ 0x19c: Master Error Address Register */ 23*af930827SMasahiro Yamada u32 res2[17]; /* 0x1A0 ~ 0x1E0 */ 24*af930827SMasahiro Yamada u32 wpmr; /* 0x1E4: Write Protection Mode Register */ 25*af930827SMasahiro Yamada u32 wpsr; /* 0x1E8: Write Protection Status Register */ 26*af930827SMasahiro Yamada u32 res3[5]; /* 0x1EC ~ 0x1FC */ 27*af930827SMasahiro Yamada u32 ssr[16]; /* 0x200 ~ 0x23c: Security Slave Register */ 28*af930827SMasahiro Yamada u32 sassr[16]; /* 0x240 ~ 0x27c: Security Areas Split Slave Register */ 29*af930827SMasahiro Yamada u32 srtsr[16]; /* 0x280 ~ 0x2bc: Security Region Top Slave */ 30*af930827SMasahiro Yamada u32 spselr[3]; /* 0x2c0 ~ 0x2c8: Security Peripheral Select Register */ 31*af930827SMasahiro Yamada }; 32*af930827SMasahiro Yamada 33*af930827SMasahiro Yamada /* Bit field in WPMR */ 34*af930827SMasahiro Yamada #define ATMEL_MATRIX_WPMR_WPKEY 0x4D415400 35*af930827SMasahiro Yamada #define ATMEL_MATRIX_WPMR_WPEN 0x00000001 36*af930827SMasahiro Yamada 37*af930827SMasahiro Yamada #endif 38